xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrFuture.td (revision 06c3fb2749bda94cb5201f81ffdb8fa6c3161b2e) 
1//===-- PPCInstrFuture.td - Future Instruction Set --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the instructions introduced for the Future CPU.
11//
12//===----------------------------------------------------------------------===//
13
14class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
15                      string asmstr, list<dag> pattern>
16         : I<opcode, OOL, IOL, asmstr, NoItinerary> {
17  bits<5> RT;
18  bits<5> RA;
19  bits<5> RB;
20  bit L;
21
22  let Pattern = pattern;
23
24  bit RC = 0;    // set by isRecordForm
25
26  let Inst{6-10}  = RT;
27  let Inst{11-15} = RA;
28  let Inst{16-20} = RB;
29  let Inst{21}    = L;
30  let Inst{22-30} = xo;
31  let Inst{31}    = RC;
32}
33
34multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
35                            string asmbase, string asmstr,
36                            list<dag> pattern> {
37  let BaseName = asmbase in {
38    def NAME : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
39                               !strconcat(asmbase, !strconcat(" ", asmstr)),
40                               pattern>, RecFormRel;
41    let Defs = [CR0] in
42    def _rec : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
43                               !strconcat(asmbase, !strconcat(". ", asmstr)),
44                               []>, isRecordForm, RecFormRel;
45  }
46}
47
48let Predicates = [IsISAFuture] in {
49  defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
50                                 (ins g8rc:$RA, g8rc:$RB, u1imm:$L),
51                                 "subfus",  "$RT, $L, $RA, $RB", []>;
52}
53
54let Predicates = [HasVSX, IsISAFuture] in {
55  let mayLoad = 1 in {
56    def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
57                              "lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
58
59    def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
60                               "lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
61
62    def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp),
63                                 (ins memr:$RA, g8rc:$RB),
64                                 "lxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
65
66    def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp),
67                                  (ins memr:$RA, g8rc:$RB),
68                                  "lxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
69  }
70
71  let mayStore = 1 in {
72    def STXVRL : XX1Form_memOp<31, 653, (outs),
73                               (ins vsrc:$XT, memr:$RA, g8rc:$RB),
74                               "stxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
75
76    def STXVRLL : XX1Form_memOp<31, 685, (outs),
77                                (ins vsrc:$XT, memr:$RA, g8rc:$RB),
78                                "stxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
79
80    def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs),
81                                  (ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
82                                  "stxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
83
84    def STXVPRLL : XForm_XTp5_XAB5<31, 749, (outs),
85                                   (ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
86                                   "stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
87  }
88}
89