181ad6265SDimitry Andric//===-- SPIRVInstrFormats.td - SPIR-V Instruction Formats --*- tablegen -*-===// 281ad6265SDimitry Andric// 381ad6265SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 481ad6265SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 581ad6265SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 681ad6265SDimitry Andric// 781ad6265SDimitry Andric//===----------------------------------------------------------------------===// 881ad6265SDimitry Andric 981ad6265SDimitry Andricdef StringImm: Operand<i32>{ 1081ad6265SDimitry Andric let PrintMethod="printStringImm"; 1181ad6265SDimitry Andric} 1281ad6265SDimitry Andric 1381ad6265SDimitry Andricclass Op<bits<16> Opcode, dag outs, dag ins, string asmstr, list<dag> pattern = []> 1481ad6265SDimitry Andric : Instruction { 1581ad6265SDimitry Andric field bits<16> Inst; 1681ad6265SDimitry Andric 1781ad6265SDimitry Andric let Inst = Opcode; 1881ad6265SDimitry Andric 1981ad6265SDimitry Andric let Namespace = "SPIRV"; 2081ad6265SDimitry Andric let DecoderNamespace = "SPIRV"; 2181ad6265SDimitry Andric 2281ad6265SDimitry Andric dag OutOperandList = outs; 2381ad6265SDimitry Andric dag InOperandList = ins; 2481ad6265SDimitry Andric let AsmString = asmstr; 2581ad6265SDimitry Andric let Pattern = pattern; 2681ad6265SDimitry Andric} 2781ad6265SDimitry Andric 2881ad6265SDimitry Andric// Pseudo instructions 2981ad6265SDimitry Andricclass Pseudo<dag outs, dag ins> : Op<0, outs, ins, ""> { 3081ad6265SDimitry Andric let isPseudo = 1; 31*bdd1243dSDimitry Andric let hasSideEffects = 0; 3281ad6265SDimitry Andric} 33