Searched refs:ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT (Results 1 – 2 of 2) sorted by relevance
364 reg |= (div1 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT) | in zy7_pl_fclk_set_freq()412 ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT; in zy7_pl_fclk_get_freq()
151 #define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT 20 macro