/freebsd/crypto/openssl/crypto/modes/asm/ |
H A D | ghashv8-armx.pl | 71 my ($Xl,$Xm,$Xh,$IN)=map("q$_",(0..3)); 137 vpmull.p64 $Xm,$t0,$t0 141 veor $Xm,$Xm,$t1 142 veor $Xm,$Xm,$t2 145 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result 146 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl 147 veor $Xl,$Xm,$t2 168 vpmull.p64 $Xm,$t0,$t1 174 veor $Xm,$Xm,$t0 177 veor $Xm,$Xm,$t2 [all …]
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H A D | ghashp8-ppc.pl | 71 my ($Xl,$Xm,$Xh,$IN)=map("v$_",(0..3)); 122 vpmsumd $Xm,$IN,$H # H.hi·H.lo+H.lo·H.hi 127 vsldoi $t0,$Xm,$zero,8 128 vsldoi $t1,$zero,$Xm,8 156 vpmsumd $Xm,$IN,$H2 # H.hi·H^2.lo+H.lo·H^2.hi 164 vsldoi $t0,$Xm,$zero,8 165 vsldoi $t1,$zero,$Xm,8 235 vpmsumd $Xm,$IN,$H # H.hi·Xi.lo+H.lo·Xi.hi 240 vsldoi $t0,$Xm,$zero,8 241 vsldoi $t1,$zero,$Xm,8 [all …]
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H A D | ghash-armv4.pl | 381 my ($Xl,$Xm,$Xh,$IN)=map("q$_",(0..3)); 500 &clmul64x64 ($Xm,$Hhl,"$IN#lo"); # (H.lo+H.hi)·(Xi.lo+Xi.hi) 503 veor $Xm,$Xm,$Xl @ Karatsuba post-processing 504 veor $Xm,$Xm,$Xh 505 veor $Xl#hi,$Xl#hi,$Xm#lo 506 veor $Xh#lo,$Xh#lo,$Xm#hi @ Xh|Xl - 256-bit result
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H A D | ghash-x86_64.pl | 704 my ($Xl,$Xm,$Xh,$Hkey3,$Hkey4)=map("%xmm$_",(11..15)); 735 pshufd \$0b01001110,$Xl,$Xm 736 pxor $Xl,$Xm 739 pclmulqdq \$0x10,$HK,$Xm 743 xorps $Xm,$Xmn 750 pshufd \$0b01001110,$Xl,$Xm 752 pxor $Xl,$Xm 758 pclmulqdq \$0x00,$HK,$Xm 770 xorps $Xm,$Xmn 778 pshufd \$0b01001110,$Xl,$Xm [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SLSHardening.cpp | 95 bool get(ThunkKind::ThunkKindId Kind, Register Xn, Register Xm) { in get() argument 97 return getBitmask(Kind, Xm) & XnBit; in get() 100 void set(ThunkKind::ThunkKindId Kind, Register Xn, Register Xm) { in set() argument 102 getBitmask(Kind, Xm) |= XnBit; in set() 121 reg_bitmask_t &getBitmask(ThunkKind::ThunkKindId Kind, Register Xm) { in getBitmask() argument 130 return BLRAAThunks[indexOfXReg(Xm)]; in getBitmask() 132 return BLRABThunks[indexOfXReg(Xm)]; in getBitmask() 280 Register Xm) { in createThunkName() argument 285 unsigned M = ThunksSet::indexOfXReg(Xm); in createThunkName() 322 Register Xm = Kind.HasXmOperand ? ParseRegName(XmStr) : AArch64::NoRegister; in parseThunkName() local [all …]
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H A D | AArch64SchedCyclone.td | 122 // ORR Xd, XZR, Xm 158 // EXAMPLE: ADDrs Xn, Xm LSL #imm 166 // EXAMPLE: ADDXre Xn, Xm, UXTB #1 178 // EXTR Xn, Xm, #imm 186 // EXTR Xn, Xm, #imm 243 // EXAMPLE: LDR Xn, Xm [, lsl 3] 249 // EXAMPLE: STR Xn, Xm [, lsl 3] 256 // EXAMPLE: LDR Xn, Xm [, lsl 3]
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H A D | AArch64InstrFormats.td | 10374 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> { 10377 bits<5> Xm; 10383 let Inst{20-16} = Xm; 10424 // "ld1\t$Vt, [$Rn], $Xm" 10426 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm) 10427 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm", 10431 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>; 10464 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>; 10469 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>; 10474 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>; [all …]
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H A D | AArch64InstrInfo.td | 2754 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>; 2758 def : InstAlias<"mvn $Xd, $Xm$sh", 2759 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>; 2778 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
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/freebsd/sys/crypto/openssl/arm/ |
H A D | ghashv8-armx.S | 50 vmov d4,d3 @ Xh|Xm - 256-bit result 51 vmov d3,d0 @ Xm is rotated Xl 89 vmov d4,d3 @ Xh|Xm - 256-bit result 90 vmov d3,d0 @ Xm is rotated Xl 185 vmov d4,d3 @ Xh|Xm - 256-bit result 186 vmov d3,d0 @ Xm is rotated Xl 222 vmov d4,d3 @ Xh|Xm - 256-bit result 223 vmov d3,d0 @ Xm is rotated Xl
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 5662 unsigned Xm = Inst.getOperand(4).getReg(); in validateInstruction() local 5672 if (Xd == Xm) in validateInstruction() 5675 if (Xn == Xm) in validateInstruction()
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