Lines Matching refs:Xm
10374 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
10377 bits<5> Xm;
10383 let Inst{20-16} = Xm;
10424 // "ld1\t$Vt, [$Rn], $Xm"
10426 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm)
10427 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
10431 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
10464 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
10469 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
10474 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
10479 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
10484 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
10489 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
10494 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
10536 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
10541 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
10546 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
10551 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
10556 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
10561 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
10566 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
10592 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
10612 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
10706 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm",
10709 (ins GPR64sp:$Rn, GPR64pi:$Xm), []> {
10710 bits<5> Xm;
10713 let Inst{20-16} = Xm;
10750 // "ld1r.8b\t$Vt, [$Rn], $Xm"
10752 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
10753 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
10757 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
10840 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
10844 bits<5> Xm;
10847 let Inst{20-16} = Xm;
10853 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
10857 bits<5> Xm;
10860 let Inst{20-16} = Xm;
10894 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
10898 bits<5> Xm;
10901 let Inst{20-16} = Xm;
10908 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
10912 bits<5> Xm;
10915 let Inst{20-16} = Xm;
10946 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
10950 bits<5> Xm;
10953 let Inst{20-16} = Xm;
10959 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
10963 bits<5> Xm;
10966 let Inst{20-16} = Xm;
10996 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
11000 bits<5> Xm;
11003 let Inst{20-16} = Xm;
11009 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
11013 bits<5> Xm;
11016 let Inst{20-16} = Xm;
11033 GPR64sp:$Rn, GPR64pi:$Xm)>;
11047 GPR64sp:$Rn, GPR64pi:$Xm)>;
11061 GPR64sp:$Rn, GPR64pi:$Xm)>;
11074 GPR64sp:$Rn, GPR64pi:$Xm)>;
11086 GPR64sp:$Rn, GPR64pi:$Xm)>;
11098 GPR64sp:$Rn, GPR64pi:$Xm)>;
11110 GPR64sp:$Rn, GPR64pi:$Xm)>;
11122 GPR64sp:$Rn, GPR64pi:$Xm)>;
11157 // "ld1.8b\t$Vt, [$Rn], $Xm"
11159 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
11160 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], $Xm",
11165 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;