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Searched refs:Writes (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp433 bool RegisterFile::tryEliminateMoveOrSwap(MutableArrayRef<WriteState> Writes, in tryEliminateMoveOrSwap() argument
435 if (Writes.size() != Reads.size()) in tryEliminateMoveOrSwap()
442 if (Writes.empty() || Writes.size() > 2) in tryEliminateMoveOrSwap()
447 RegisterMappings[Writes[0].getRegisterID()].second; in tryEliminateMoveOrSwap()
453 (RMT.NumMoveEliminated + Writes.size()) > RMT.MaxMoveEliminatedPerCycle) in tryEliminateMoveOrSwap()
456 for (size_t I = 0, E = Writes.size(); I < E; ++I) { in tryEliminateMoveOrSwap()
458 const WriteState &WS = Writes[E - (I + 1)]; in tryEliminateMoveOrSwap()
463 for (size_t I = 0, E = Writes.size(); I < E; ++I) { in tryEliminateMoveOrSwap()
465 WriteState &WS = Writes[E - (I + 1)]; in tryEliminateMoveOrSwap()
512 SmallVectorImpl<WriteRef> &Writes, in collectWrites() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/DWARFCFIChecker/
H A DDWARFCFIAnalysis.cpp137 SmallSet<DWARFRegNum, 4> Writes, Reads; in update() local
142 Writes.insert(MCRI->getDwarfRegNum( in update()
149 Writes.insert( in update()
161 checkCFADiff(Inst, PrevRow, NextRow, Reads, Writes); in update()
166 checkRegDiff(Inst, Reg, PrevRow, NextRow, Reads, Writes); in update()
174 const SmallSet<DWARFRegNum, 4> &Writes) { in checkRegDiff() argument
211 if (Writes.count(UsedReg)) { // Case 1.b in checkRegDiff()
244 if (Writes.count(UsedReg)) { // Case 2.c.i in checkRegDiff()
264 const SmallSet<DWARFRegNum, 4> &Writes) { in checkCFADiff() argument
300 if (!Writes.count(PrevCFA.Reg)) // Case 1.a in checkCFADiff()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57.td67 list <SchedWriteRes> Writes = writes;
530 SchedVar<A57LMAddrPred1, A57LDMOpsListNoregin.Writes[0-1]>,
531 SchedVar<A57LMAddrPred2, A57LDMOpsListNoregin.Writes[0-3]>,
532 SchedVar<A57LMAddrPred3, A57LDMOpsListNoregin.Writes[0-5]>,
533 SchedVar<A57LMAddrPred4, A57LDMOpsListNoregin.Writes[0-7]>,
534 SchedVar<A57LMAddrPred5, A57LDMOpsListNoregin.Writes[0-9]>,
535 SchedVar<A57LMAddrPred6, A57LDMOpsListNoregin.Writes[0-11]>,
536 SchedVar<A57LMAddrPred7, A57LDMOpsListNoregin.Writes[0-13]>,
537 SchedVar<A57LMAddrPred8, A57LDMOpsListNoregin.Writes[0-15]>,
538 SchedVar<NoSchedPred, A57LDMOpsListNoregin.Writes[0-15]>
[all …]
H A DARMScheduleA9.td1882 list <WriteSequence> Writes = writes;
2110 SchedVar<A9LMAdr1Pred, A9WriteLMOpsList.Writes[0-1]>,
2111 SchedVar<A9LMAdr2Pred, A9WriteLMOpsList.Writes[0-3]>,
2112 SchedVar<A9LMAdr3Pred, A9WriteLMOpsList.Writes[0-5]>,
2113 SchedVar<A9LMAdr4Pred, A9WriteLMOpsList.Writes[0-7]>,
2114 SchedVar<A9LMAdr5Pred, A9WriteLMOpsList.Writes[0-9]>,
2115 SchedVar<A9LMAdr6Pred, A9WriteLMOpsList.Writes[0-11]>,
2116 SchedVar<A9LMAdr7Pred, A9WriteLMOpsList.Writes[0-13]>,
2117 SchedVar<A9LMAdr8Pred, A9WriteLMOpsList.Writes[0-15]>,
2215 SchedVar<A9LMAdr1Pred, A9WriteLMfpPostRAOpsList.Writes[
[all...]
H A DARMParallelDSP.cpp341 SmallVector<Instruction*, 8> Writes; in RecordMemoryOps() local
350 Writes.push_back(&I); in RecordMemoryOps()
367 for (auto *Write : Writes) { in RecordMemoryOps()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenSchedule.cpp732 void CodeGenSchedModels::findRWs(const ConstRecVec &RWDefs, IdxVec &Writes, in findRWs() argument
737 findRWs(WriteDefs, Writes, false); in findRWs()
841 IdxVec Writes, Reads; in collectSchedClasses() local
843 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); in collectSchedClasses()
846 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/ {0}); in collectSchedClasses()
886 if (!SC.Writes.empty()) { in collectSchedClasses()
890 for (unsigned int Write : SC.Writes) in collectSchedClasses()
903 IdxVec Writes; in collectSchedClasses() local
905 findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads); in collectSchedClasses()
907 for (unsigned WIdx : Writes) in collectSchedClasses()
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H A DCodeGenSchedule.h136 IdxVec Writes; member
157 return ItinClassDef == IC && ArrayRef(Writes) == W && ArrayRef(Reads) == R; in isKeyEqual()
553 void findRWs(const ConstRecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
630 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCInstrAnalysis.cpp22 APInt &Writes) const { in clearsSuperRegisters()
23 Writes.clearAllBits(); in clearsSuperRegisters()
/freebsd/contrib/llvm-project/llvm/include/llvm/DWARFCFIChecker/
H A DDWARFCFIAnalysis.h89 const SmallSet<DWARFRegNum, 4> &Writes);
94 const SmallSet<DWARFRegNum, 4> &Writes);
/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DInstrBuilder.cpp325 ID.Writes.resize(TotalDefs + NumVariadicOps); in populateWrites()
346 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
373 WriteDescriptor &Write = ID.Writes[Index]; in populateWrites()
400 WriteDescriptor &Write = ID.Writes[NumExplicitDefs + NumImplicitDefs]; in populateWrites()
426 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
440 ID.Writes.resize(CurrentDef); in populateWrites()
782 if (D.Writes.empty()) { in createInstruction()
791 APInt WriteMask(D.Writes.size(), 0); in createInstruction()
801 for (const WriteDescriptor &WD : D.Writes) { in createInstruction()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCalcSpillWeights.cpp277 bool Reads, Writes; in weightCalcHelper() local
278 std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg()); in weightCalcHelper()
279 Weight = LiveIntervals::getSpillWeight(Writes, Reads, &MBFI, *MI, PSI); in weightCalcHelper()
282 if (Writes && IsExiting && LIS.isLiveOutOfMBB(LI, MBB)) in weightCalcHelper()
H A DMLRegallocEvictAdvisor.cpp
H A DMLRegAllocEvictAdvisor.cpp909 bool Reads, Writes; in getLIFeatureComponents() local
910 std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg()); in getLIFeatureComponents()
915 Ret.R += (Reads && !Writes) * Freq; in getLIFeatureComponents()
916 Ret.W += (!Reads && Writes) * Freq; in getLIFeatureComponents()
917 Ret.RW += (Reads && Writes) * Freq; in getLIFeatureComponents()
923 if (Writes && IsExiting && LIS->isLiveOutOfMBB(LI, MBB)) in getLIFeatureComponents()
H A DMachineInstrBundle.cpp279 RI.Writes = true; in AnalyzeVirtRegInBundle()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopDataPrefetch.cpp239 bool Writes = false; member
257 Writes = isa<StoreInst>(I); in addInstruction()
268 Writes = true; in addInstruction()
407 {PrefPtrValue, ConstantInt::get(I32, P.Writes), in runOnLoop()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h237 SmallVectorImpl<WriteRef> &Writes,
278 bool tryEliminateMoveOrSwap(MutableArrayRef<WriteState> Writes,
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h377 void setDependentWrites(unsigned Writes) { in setDependentWrites() argument
378 DependentWrites = Writes; in setDependentWrites()
379 IsReady = !Writes; in setDependentWrites()
449 SmallVector<WriteDescriptor, 2> Writes; // Implicit writes are at the end. member
/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A DELF_riscv.cpp497 SmallVector<uint32_t, 0> Writes; member
605 Aux.Writes.push_back(0xa001); // c.j in relaxCall()
609 Aux.Writes.push_back(0x2001); // c.jal in relaxCall()
613 Aux.Writes.push_back(0x6f | RD << 7); // jal in relaxCall()
630 Aux.Writes.clear(); in relaxBlock()
686 auto NextWrite = Aux.Writes.begin(); in finalizeBlockRelax()
H A DELF_loongarch.cpp70 SmallVector<uint32_t, 0> Writes; member
168 Aux.Writes.clear(); in relaxBlock()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsARM.td118 // Writes to the GE bits.
127 // Writes to the GE bits.
130 // Writes to the GE bits.
145 // Writes to the GE bits.
171 // Writes to the GE bits.
174 // Writes to the GE bits.
189 // Writes to the GE bits.
192 // Writes to the GE bits.
195 // Writes to the GE bits.
198 // Writes to the GE bits.
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp1066 IdxVec Writes = SC.Writes; in genSchedClassTables() local
1080 Writes.clear(); in genSchedClassTables()
1083 Writes, Reads); in genSchedClassTables()
1086 if (Writes.empty()) { in genSchedClassTables()
1092 Writes, Reads); in genSchedClassTables()
1096 if (Writes.empty()) { in genSchedClassTables()
1108 for (unsigned W : Writes) { in genSchedClassTables()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h118 APInt &Writes) const;
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBundle.h226 bool Writes; member
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp620 bool Reads, Writes; in SafeInFPUDelaySlot() local
621 std::tie(Reads, Writes) = MIInSlot.readsWritesVirtualRegister(Op.getReg()); in SafeInFPUDelaySlot()
623 if (Reads || Writes) in SafeInFPUDelaySlot()
/freebsd/sys/dev/ath/ath_hal/ar9001/
H A Dar9160.ini17 /* Auto Generated PCI Register Writes. Created: 05/22/08 */
631 /* Auto generated PCI Register Writes for SOWL1.0 ADDAC Shift Chain */
667 /* Auto generated PCI Register Writes for SOWL1.1 ADDAC Shift Chain */

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