Lines Matching refs:Writes
67 list <SchedWriteRes> Writes = writes;
530 SchedVar<A57LMAddrPred1, A57LDMOpsListNoregin.Writes[0-1]>,
531 SchedVar<A57LMAddrPred2, A57LDMOpsListNoregin.Writes[0-3]>,
532 SchedVar<A57LMAddrPred3, A57LDMOpsListNoregin.Writes[0-5]>,
533 SchedVar<A57LMAddrPred4, A57LDMOpsListNoregin.Writes[0-7]>,
534 SchedVar<A57LMAddrPred5, A57LDMOpsListNoregin.Writes[0-9]>,
535 SchedVar<A57LMAddrPred6, A57LDMOpsListNoregin.Writes[0-11]>,
536 SchedVar<A57LMAddrPred7, A57LDMOpsListNoregin.Writes[0-13]>,
537 SchedVar<A57LMAddrPred8, A57LDMOpsListNoregin.Writes[0-15]>,
538 SchedVar<NoSchedPred, A57LDMOpsListNoregin.Writes[0-15]>
551 SchedVar<A57LMAddrPred1, A57LDMOpsListRegin.Writes[0-1]>,
552 SchedVar<A57LMAddrPred2, A57LDMOpsListRegin.Writes[0-3]>,
553 SchedVar<A57LMAddrPred3, A57LDMOpsListRegin.Writes[0-5]>,
554 SchedVar<A57LMAddrPred4, A57LDMOpsListRegin.Writes[0-7]>,
555 SchedVar<A57LMAddrPred5, A57LDMOpsListRegin.Writes[0-9]>,
556 SchedVar<A57LMAddrPred6, A57LDMOpsListRegin.Writes[0-11]>,
557 SchedVar<A57LMAddrPred7, A57LDMOpsListRegin.Writes[0-13]>,
558 SchedVar<A57LMAddrPred8, A57LDMOpsListRegin.Writes[0-15]>,
559 SchedVar<NoSchedPred, A57LDMOpsListRegin.Writes[0-15]>
573 SchedVar<A57LMAddrUpdPred1, A57LDMOpsList_Upd.Writes[0-2]>,
574 SchedVar<A57LMAddrUpdPred2, A57LDMOpsList_Upd.Writes[0-4]>,
575 SchedVar<A57LMAddrUpdPred3, A57LDMOpsList_Upd.Writes[0-6]>,
576 SchedVar<A57LMAddrUpdPred4, A57LDMOpsList_Upd.Writes[0-8]>,
577 SchedVar<A57LMAddrUpdPred5, A57LDMOpsList_Upd.Writes[0-10]>,
578 SchedVar<A57LMAddrUpdPred6, A57LDMOpsList_Upd.Writes[0-12]>,
579 SchedVar<A57LMAddrUpdPred7, A57LDMOpsList_Upd.Writes[0-14]>,
580 SchedVar<A57LMAddrUpdPred8, A57LDMOpsList_Upd.Writes[0-16]>,
581 SchedVar<NoSchedPred, A57LDMOpsList_Upd.Writes[0-16]>
826 SchedVar<A57LMAddrPred1, A57VLDMOpsListUncond.Writes[0-1]>,
827 SchedVar<A57LMAddrPred2, A57VLDMOpsListUncond.Writes[0-3]>,
828 SchedVar<A57LMAddrPred3, A57VLDMOpsListUncond.Writes[0-5]>,
829 SchedVar<A57LMAddrPred4, A57VLDMOpsListUncond.Writes[0-7]>,
830 SchedVar<A57LMAddrPred5, A57VLDMOpsListUncond.Writes[0-9]>,
831 SchedVar<A57LMAddrPred6, A57VLDMOpsListUncond.Writes[0-11]>,
832 SchedVar<A57LMAddrPred7, A57VLDMOpsListUncond.Writes[0-13]>,
833 SchedVar<NoSchedPred, A57VLDMOpsListUncond.Writes[0-15]>
846 SchedVar<A57LMAddrPred1, A57VLDMOpsListCond.Writes[0-1]>,
847 SchedVar<A57LMAddrPred2, A57VLDMOpsListCond.Writes[0-3]>,
848 SchedVar<A57LMAddrPred3, A57VLDMOpsListCond.Writes[0-5]>,
849 SchedVar<A57LMAddrPred4, A57VLDMOpsListCond.Writes[0-7]>,
850 SchedVar<A57LMAddrPred5, A57VLDMOpsListCond.Writes[0-9]>,
851 SchedVar<A57LMAddrPred6, A57VLDMOpsListCond.Writes[0-11]>,
852 SchedVar<A57LMAddrPred7, A57VLDMOpsListCond.Writes[0-13]>,
853 SchedVar<NoSchedPred, A57VLDMOpsListCond.Writes[0-15]>
873 SchedVar<A57LMAddrPred1, A57VLDMOpsListUncond_Upd.Writes[0-1]>,
874 SchedVar<A57LMAddrPred2, A57VLDMOpsListUncond_Upd.Writes[0-3]>,
875 SchedVar<A57LMAddrPred3, A57VLDMOpsListUncond_Upd.Writes[0-5]>,
876 SchedVar<A57LMAddrPred4, A57VLDMOpsListUncond_Upd.Writes[0-7]>,
877 SchedVar<A57LMAddrPred5, A57VLDMOpsListUncond_Upd.Writes[0-9]>,
878 SchedVar<A57LMAddrPred6, A57VLDMOpsListUncond_Upd.Writes[0-11]>,
879 SchedVar<A57LMAddrPred7, A57VLDMOpsListUncond_Upd.Writes[0-13]>,
880 SchedVar<NoSchedPred, A57VLDMOpsListUncond_Upd.Writes[0-15]>
893 SchedVar<A57LMAddrPred1, A57VLDMOpsListCond_Upd.Writes[0-1]>,
894 SchedVar<A57LMAddrPred2, A57VLDMOpsListCond_Upd.Writes[0-3]>,
895 SchedVar<A57LMAddrPred3, A57VLDMOpsListCond_Upd.Writes[0-5]>,
896 SchedVar<A57LMAddrPred4, A57VLDMOpsListCond_Upd.Writes[0-7]>,
897 SchedVar<A57LMAddrPred5, A57VLDMOpsListCond_Upd.Writes[0-9]>,
898 SchedVar<A57LMAddrPred6, A57VLDMOpsListCond_Upd.Writes[0-11]>,
899 SchedVar<A57LMAddrPred7, A57VLDMOpsListCond_Upd.Writes[0-13]>,
900 SchedVar<NoSchedPred, A57VLDMOpsListCond_Upd.Writes[0-15]>