Home
last modified time | relevance | path

Searched refs:WRITE4 (Results 1 – 25 of 48) sorted by relevance

12

/freebsd/sys/arm/freescale/vybrid/
H A Dvf_dcu4.c229 WRITE4(sc, DCU_INT_STATUS, reg); in dcu_intr()
294 WRITE4(sc, DCU_DISP_SIZE, reg); in dcu_init()
299 WRITE4(sc, DCU_HSYN_PARA, reg); in dcu_init()
304 WRITE4(sc, DCU_VSYN_PARA, reg); in dcu_init()
306 WRITE4(sc, DCU_BGND, 0); in dcu_init()
307 WRITE4(sc, DCU_DIV_RATIO, panel->clk_div); in dcu_init()
310 WRITE4(sc, DCU_SYNPOL, reg); in dcu_init()
316 WRITE4(sc, DCU_THRESHOLD, reg); in dcu_init()
319 WRITE4(sc, DCU_INT_MASK, 0xffffffff); in dcu_init()
323 WRITE4(sc, DCU_CTRLDESCLn_1(i), 0x0); in dcu_init()
[all …]
H A Dvf_anadig.c140 WRITE4(sc, pll_ctrl, reg); in enable_pll()
148 WRITE4(sc, pll_ctrl, reg); in enable_pll()
168 WRITE4(sc, ANADIG_PLL4_CTRL, reg); in pll4_configure_output()
169 WRITE4(sc, ANADIG_PLL4_NUM, mfn); in pll4_configure_output()
170 WRITE4(sc, ANADIG_PLL4_DENOM, mfd); in pll4_configure_output()
208 WRITE4(sc, ANADIG_REG_3P0, reg); in anadig_attach()
213 WRITE4(sc, USB_MISC(0), reg); in anadig_attach()
217 WRITE4(sc, USB_MISC(1), reg); in anadig_attach()
H A Dvf_spi.c166 WRITE4(sc, SPI_MCR, reg); in spi_attach()
170 WRITE4(sc, SPI_RSER, reg); in spi_attach()
174 WRITE4(sc, SPI_MCR, reg); in spi_attach()
192 WRITE4(sc, SPI_CTAR0, reg); in spi_attach()
197 WRITE4(sc, SPI_CTAR0, reg); in spi_attach()
223 WRITE4(sc, SPI_PUSHR, wreg); in spi_txrx()
234 WRITE4(sc, SPI_SR, reg); in spi_txrx()
H A Dvf_adc.c171 WRITE4(sc, ADC_HC0, reg); in adc_enable()
208 WRITE4(sc, ADC_CFG, reg); in adc_attach()
213 WRITE4(sc, ADC_GC, reg); in adc_attach()
218 WRITE4(sc, ADC_HC0, reg); in adc_attach()
H A Dvf_sai.c358 WRITE4(sc, I2S_TCR2, reg); in sai_configure_clock()
623 WRITE4(sc, I2S_TCSR, reg); in setup_sai()
627 WRITE4(sc, I2S_TCR3, reg); in setup_sai()
630 WRITE4(sc, I2S_TCR1, reg); in setup_sai()
636 WRITE4(sc, I2S_TCR2, reg); in setup_sai()
642 WRITE4(sc, I2S_TCR3, reg); in setup_sai()
651 WRITE4(sc, I2S_TCR4, reg); in setup_sai()
660 WRITE4(sc, I2S_TCR5, reg); in setup_sai()
666 WRITE4(sc, I2S_TCSR, reg); in setup_sai()
/freebsd/sys/dev/flash/
H A Dcqspi.c83 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro
159 WRITE4(sc, CQSPI_IRQSTAT, pending); in cqspi_intr()
260 WRITE4(sc, CQSPI_FLASHCMDADDR, addr); in cqspi_cmd_write_addr()
264 WRITE4(sc, CQSPI_FLASHCMD, reg); in cqspi_cmd_write_addr()
267 WRITE4(sc, CQSPI_FLASHCMD, reg); in cqspi_cmd_write_addr()
282 WRITE4(sc, CQSPI_FLASHCMD, reg); in cqspi_cmd_write()
284 WRITE4(sc, CQSPI_FLASHCMD, reg); in cqspi_cmd_write()
313 WRITE4(sc, CQSPI_FLASHCMD, reg); in cqspi_cmd_read()
316 WRITE4(sc, CQSPI_FLASHCMD, reg); in cqspi_cmd_read()
429 WRITE4(sc, CQSPI_DMAPER, reg); in cqspi_write()
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_sdma.c64 #define WRITE4(_sc, _reg, _val) \ macro
97 WRITE4(sc, SDMAARM_INTR, pending); in sdma_intr()
115 WRITE4(sc, SDMAARM_HSTART, (1 << i)); in sdma_intr()
140 WRITE4(sc, SDMAARM_HSTART, (1 << chn)); in sdma_start()
152 WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn)); in sdma_stop()
219 WRITE4(sc, SDMAARM_EVTOVR, reg); in sdma_overrides()
227 WRITE4(sc, SDMAARM_HOSTOVR, reg); in sdma_overrides()
235 WRITE4(sc, SDMAARM_DSPOVR, reg); in sdma_overrides()
263 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); in sdma_configure()
264 WRITE4(sc, SDMAARM_CHNENBL(conf->event), (1 << chn)); in sdma_configure()
[all …]
H A Dimx_gpt.c50 #define WRITE4(_sc, _r, _v) \ macro
55 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
57 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
191 WRITE4(sc, IMX_GPT_CR, 0); in imx_gpt_attach()
192 WRITE4(sc, IMX_GPT_IR, 0); in imx_gpt_attach()
202 WRITE4(sc, IMX_GPT_CR, ctlreg); in imx_gpt_attach()
212 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); in imx_gpt_attach()
225 WRITE4(sc, IMX_GPT_PR, prescale); in imx_gpt_attach()
228 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); in imx_gpt_attach()
231 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); in imx_gpt_attach()
[all …]
H A Dimx_gpio.c71 #define WRITE4(_sc, _r, _v) \ macro
76 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
78 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
311 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << gi->gi_irq)); in gpio_pic_teardown_intr()
383 WRITE4(sc, reg, wrk); in gpio_pic_setup_intr()
385 WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq)); in gpio_pic_setup_intr()
437 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); in gpio_pic_post_filter()
451 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); in gpio_pic_post_ithread()
708 WRITE4(sc, IMX_GPIO_DR_REG, in imx51_gpio_pin_toggle()
731 WRITE4(sc, IMX_GPIO_DR_REG, in imx51_gpio_pin_access_32()
[all …]
H A Dimx6_audmux.c54 #define WRITE4(_sc, _reg, _val) \ macro
105 WRITE4(sc, AUDMUX_PTCR(audmux_port), reg); in audmux_configure()
109 WRITE4(sc, AUDMUX_PDCR(audmux_port), reg); in audmux_configure()
/freebsd/sys/dev/dwc/
H A Ddwc1000_core.c103 WRITE4(sc, GMII_ADDRESS, mii); in dwc1000_miibus_read_reg()
130 WRITE4(sc, GMII_DATA, val); in dwc1000_miibus_write_reg()
131 WRITE4(sc, GMII_ADDRESS, mii); in dwc1000_miibus_write_reg()
192 WRITE4(sc, MAC_CONFIGURATION, reg); in dwc1000_miibus_statchg()
201 WRITE4(sc, FLOW_CONTROL, reg); in dwc1000_miibus_statchg()
217 WRITE4(sc, MAC_CONFIGURATION, reg); in dwc1000_core_setup()
231 WRITE4(sc, MAC_CONFIGURATION, reg); in dwc1000_enable_mac()
245 WRITE4(sc, MAC_CONFIGURATION, reg); in dwc1000_enable_csum_offload()
342 WRITE4(sc, MAC_ADDRESS_LOW(0), lo); in dwc1000_setup_rxfilter()
343 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); in dwc1000_setup_rxfilter()
[all …]
H A Ddwc1000_dma.c505 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); in dma1000_txstart()
556 WRITE4(sc, OPERATION_MODE, reg); in dma1000_start()
558 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); in dma1000_start()
563 WRITE4(sc, OPERATION_MODE, reg); in dma1000_start()
579 WRITE4(sc, OPERATION_MODE, reg); in dma1000_stop()
584 WRITE4(sc, OPERATION_MODE, reg); in dma1000_stop()
589 WRITE4(sc, OPERATION_MODE, reg); in dma1000_stop()
600 WRITE4(sc, BUS_MODE, reg); in dma1000_reset()
638 WRITE4(sc, BUS_MODE, reg); in dma1000_init()
649 WRITE4(sc, OPERATION_MODE, reg); in dma1000_init()
[all …]
/freebsd/sys/dev/mmc/host/
H A Ddwmmc.c90 #define WRITE4(_sc, _reg, _val) \ macro
216 WRITE4(sc, SDMMC_CTRL, reg); in dwmmc_ctrl_reset()
426 WRITE4(sc, SDMMC_RINTSTS, reg); in dwmmc_intr()
441 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI | in dwmmc_intr()
443 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI); in dwmmc_intr()
722 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr); in dwmmc_attach()
725 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK); in dwmmc_attach()
726 WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI | in dwmmc_attach()
732 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); in dwmmc_attach()
733 WRITE4(sc, SDMMC_INTMASK, 0); in dwmmc_attach()
[all …]
H A Ddwmmc_samsung.c45 #define WRITE4(_sc, _reg, _val) \ macro
101 WRITE4(sc, EMMCP_MPSBEGIN0, 0); in samsung_dwmmc_attach()
102 WRITE4(sc, EMMCP_SEND0, 0); in samsung_dwmmc_attach()
103 WRITE4(sc, EMMCP_CTRL0, (MPSCTRL_SECURE_READ_BIT | in samsung_dwmmc_attach()
/freebsd/sys/dev/xilinx/
H A Daxi_quad_spi.c66 #define WRITE4(_sc, _reg, _val) \ macro
140 WRITE4(sc, SPI_SRR, SRR_RESET); in spi_attach()
145 WRITE4(sc, SPI_CR, reg); in spi_attach()
146 WRITE4(sc, SPI_DGIER, 0); /* Disable interrupts */ in spi_attach()
149 WRITE4(sc, SPI_CR, reg); in spi_attach()
164 WRITE4(sc, SPI_DTR, out_buf[i]); in spi_txrx()
199 WRITE4(sc, SPI_SSR, reg); in spi_transfer()
210 WRITE4(sc, SPI_SSR, reg); in spi_transfer()
H A Dif_xae.c70 #define WRITE4(_sc, _reg, _val) \ macro
349 WRITE4(sc, XAE_TC, reg); in xae_stop_locked()
354 WRITE4(sc, XAE_RCW1, reg); in xae_stop_locked()
450 WRITE4(sc, XAE_TC, TC_TX); in xae_init_locked()
453 WRITE4(sc, XAE_RCW1, RCW1_RX); in xae_init_locked()
527 WRITE4(sc, XAE_FFC, reg); in xae_write_maddr()
533 WRITE4(sc, XAE_FFV(0), reg); in xae_write_maddr()
537 WRITE4(sc, XAE_FFV(1), reg); in xae_write_maddr()
558 WRITE4(sc, XAE_FFC, reg); in xae_setup_rxfilter()
562 WRITE4(sc, XAE_FFC, reg); in xae_setup_rxfilter()
[all …]
/freebsd/sys/dev/clk/rockchip/
H A Drk_clk_pll.c53 #define WRITE4(_clk, off, val) \ macro
89 WRITE4(clk, sc->gate_offset, val); in rk_clk_pll_set_gate()
150 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_mux()
231 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
234 WRITE4(clk, sc->base_offset + 12, RK3066_CLK_PLL_RESET | in rk3066_clk_pll_set_freq()
246 WRITE4(clk, sc->base_offset, reg); in rk3066_clk_pll_set_freq()
256 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3066_clk_pll_set_freq()
261 WRITE4(clk, sc->base_offset + 0x8, reg); in rk3066_clk_pll_set_freq()
264 WRITE4(clk, sc->base_offset + 12, in rk3066_clk_pll_set_freq()
290 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Daw_clk_nkmp.c62 #define WRITE4(_clk, off, val) \ macro
111 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_gate()
132 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_mux()
205 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
212 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
220 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
226 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
233 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
293 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq()
301 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq()
H A Daw_clk_mipi.c65 #define WRITE4(_clk, off, val) \ macro
106 WRITE4(clk, sc->offset, val); in aw_clk_mipi_set_gate()
175 WRITE4(clk, sc->offset, val); in aw_clk_mipi_set_freq()
188 WRITE4(clk, sc->offset, val); in aw_clk_mipi_set_freq()
192 WRITE4(clk, sc->offset, val); in aw_clk_mipi_set_freq()
H A Daw_clk_frac.c67 #define WRITE4(_clk, off, val) \ macro
116 WRITE4(clk, sc->offset, val); in aw_clk_frac_set_gate()
138 WRITE4(clk, sc->offset, val); in aw_clk_frac_set_mux()
267 WRITE4(clk, sc->offset, val); in aw_clk_frac_set_freq()
288 WRITE4(clk, sc->offset, val); in aw_clk_frac_set_freq()
292 WRITE4(clk, sc->offset, val); in aw_clk_frac_set_freq()
H A Daw_clk_m.c59 #define WRITE4(_clk, off, val) \ macro
106 WRITE4(clk, sc->offset, val); in aw_clk_m_set_gate()
127 WRITE4(clk, sc->offset, val); in aw_clk_m_set_mux()
213 WRITE4(clk, sc->offset, val); in aw_clk_m_set_freq()
/freebsd/sys/arm/ti/clk/
H A Dti_clk_clkctrl.c70 #define WRITE4(_clk, off, val) \ macro
114 WRITE4(clk, sc->register_offset, val); in ti_clkctrl_set_gdbclk_gate()
153 WRITE4(clk, sc->register_offset, MODULEMODE_ENABLE); in ti_clkctrl_set_gate()
155 WRITE4(clk, sc->register_offset, MODULEMODE_DISABLE); in ti_clkctrl_set_gate()
/freebsd/sys/dev/agp/
H A Dagp_ati.c58 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) macro
228 WRITE4(ATI_GART_FEATURE_ID, 0x00060000); in agp_ati_attach()
233 WRITE4(ATI_GART_BASE, sc->ag_pdir); in agp_ati_attach()
254 WRITE4(ATI_GART_BASE, 0); in agp_ati_detach()
341 WRITE4(ATI_GART_CACHE_CNTRL, 1); in agp_ati_flush_tlb()
H A Dagp_amd.c58 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) macro
249 WRITE4(AGP_AMD751_ATTBASE, gatt->ag_pdir); in agp_amd_attach()
284 WRITE4(AGP_AMD751_ATTBASE, 0); in agp_amd_detach()
367 WRITE4(AGP_AMD751_TLBCTRL, 1); in agp_amd_flush_tlb()
/freebsd/sys/dev/xdma/controller/
H A Dpl330.c77 #define WRITE4(_sc, _reg, _val) \ macro
170 WRITE4(sc, INTCLR, pending); in pl330_intr()
550 WRITE4(sc, DBGINST0, reg); in pl330_channel_submit_sg()
552 WRITE4(sc, DBGINST1, reg); in pl330_channel_submit_sg()
554 WRITE4(sc, INTCLR, 0xffffffff); in pl330_channel_submit_sg()
555 WRITE4(sc, INTEN, (1 << chan->index)); in pl330_channel_submit_sg()
561 WRITE4(sc, DBGCMD, 0); in pl330_channel_submit_sg()

12