Lines Matching refs:WRITE4
53 #define WRITE4(_clk, off, val) \ macro
89 WRITE4(clk, sc->gate_offset, val); in rk_clk_pll_set_gate()
150 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_mux()
231 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
234 WRITE4(clk, sc->base_offset + 12, RK3066_CLK_PLL_RESET | in rk3066_clk_pll_set_freq()
246 WRITE4(clk, sc->base_offset, reg); in rk3066_clk_pll_set_freq()
256 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3066_clk_pll_set_freq()
261 WRITE4(clk, sc->base_offset + 0x8, reg); in rk3066_clk_pll_set_freq()
264 WRITE4(clk, sc->base_offset + 12, in rk3066_clk_pll_set_freq()
290 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
454 WRITE4(clk, sc->mode_reg, reg); in rk3328_clk_pll_set_freq()
461 WRITE4(clk, sc->base_offset, reg); in rk3328_clk_pll_set_freq()
471 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3328_clk_pll_set_freq()
478 WRITE4(clk, sc->base_offset + 0x8, reg); in rk3328_clk_pll_set_freq()
493 WRITE4(clk, sc->mode_reg, reg); in rk3328_clk_pll_set_freq()
694 WRITE4(clk, sc->base_offset + 0xC, reg); in rk3399_clk_pll_set_freq()
699 WRITE4(clk, sc->base_offset, reg); in rk3399_clk_pll_set_freq()
707 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3399_clk_pll_set_freq()
713 WRITE4(clk, sc->base_offset + 0x8, reg | RK3399_CLK_PLL_WRITE_MASK); in rk3399_clk_pll_set_freq()
718 WRITE4(clk, sc->base_offset + 0xC, reg); in rk3399_clk_pll_set_freq()
731 WRITE4(clk, sc->base_offset + 0xC, reg); in rk3399_clk_pll_set_freq()