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Searched refs:VR128 (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrXOP.td14 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
16 [(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[SchedWriteVecALU.XMM]>;
17 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
19 [(set VR128:$dst, (Int (load addr:$src)))]>, XOP,
45 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
47 [(set VR128:$dst, (Int VR128
[all...]
H A DX86InstrSSE.td121 def FsFLD0F128 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
122 [(set VR128:$dst, fp128imm0)]>, Requires<[HasSSE1, NoAVX512]>;
136 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
137 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
173 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
174 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
197 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
198 (ins VR128:$src1, VR128:$src2),
200 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))], d>,
205 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
[all …]
H A DX86InstrVecCompiler.td20 def : Pat<(f16 (extractelt (v8f16 VR128:$src), (iPTR 0))),
21 (COPY_TO_REGCLASS (v8f16 VR128:$src), FR16)>;
22 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
23 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
24 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
25 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
40 (COPY_TO_REGCLASS FR16:$src, VR128)>;
43 (COPY_TO_REGCLASS FR32:$src, VR128)>;
46 (COPY_TO_REGCLASS FR64:$src, VR128)>;
79 defm : subvector_subreg_lowering<VR128, v4i3
[all...]
H A DX86InstrKL.td22 def AESENC128KL#suffix : I<0xDC, MRMSrcMem, (outs VR128:$dst),
23 (ins VR128:$src1, opaquemem:$src2),
25 [(set VR128:$dst, EFLAGS, (X86aesenc128kl VR128:$src1, addr:$src2))]>,
27 def AESDEC128KL#suffix : I<0xDD, MRMSrcMem, (outs VR128:$dst),
28 (ins VR128:$src1, opaquemem:$src2),
30 [(set VR128:$dst, EFLAGS, (X86aesdec128kl VR128:$src1, addr:$src2))]>,
32 def AESENC256KL#suffix : I<0xDE, MRMSrcMem, (outs VR128:$dst),
33 (ins VR128:$src1, opaquemem:$src2),
35 [(set VR128:$dst, EFLAGS, (X86aesenc256kl VR128:$src1, addr:$src2))]>,
37 def AESDEC256KL#suffix : I<0xDF, MRMSrcMem, (outs VR128:$dst),
[all …]
H A DX86InstrFMA.td106 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>;
108 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>;
110 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>;
313 VR128, ssmem, sched>;
319 VR128, sdmem, sched>, REX_W;
336 def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector
338 (EltVT (extractelt (VT VR128:$src1), (iPTR 0))),
341 VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)),
342 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>;
344 def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector
[all …]
H A DX86InstrMMX.td234 (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}",
236 (x86mmx (MMX_X86movdq2q VR128:$src)))]>;
238 def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
240 [(set VR128:$dst,
488 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
491 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
494 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
497 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
500 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
504 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
[all...]
H A DX86InstrCompiler.td597 defm _VR128 : CMOVrr_PSEUDO<VR128, v2i64>;
614 def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
615 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;
618 def : Pat<(v16i8 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
619 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;
620 def : Pat<(v8i16 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
621 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;
622 def : Pat<(v4i32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
623 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;
624 def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
[all …]
H A DX86GenRegisterBankInfo.def24 // VR128/256/512
H A DX86InstrOperands.td100 def vx64mem : X86VMemOperand<VR128, "printqwordmem", X86Mem64_RC128Operand, 64>;
101 def vx128mem : X86VMemOperand<VR128, "printxmmwordmem", X86Mem128_RC128Operand, 128>;
102 def vx256mem : X86VMemOperand<VR128, "printymmwordmem", X86Mem256_RC128Operand, 256>;
H A DX86RegisterInfo.td768 // Generic vector registers: VR64 and VR128.
771 def VR128 : RegisterClass<"X86", [v4f32, v2f64, v8f16, v8bf16, v16i8, v8i16, v4i32, v2i64, f128],
805 // Extended VR128 and VR256 for AVX-512 instructions
H A DX86FastISel.cpp2226 const TargetRegisterClass *VR128 = &X86::VR128RegClass; in X86FastEmitSSESelect() local
2240 Register VBlendReg = fastEmitInst_rrr(BlendOpcode, VR128, RHSReg, LHSReg, in X86FastEmitSSESelect()
2259 const TargetRegisterClass *VR128 = &X86::VR128RegClass; in X86FastEmitSSESelect() local
2261 Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, LHSReg); in X86FastEmitSSESelect()
2262 Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg, RHSReg); in X86FastEmitSSESelect()
2263 Register OrReg = fastEmitInst_rr(Opc[3], VR128, AndNReg, AndReg); in X86FastEmitSSESelect()
H A DX86InstrAsmAlias.td901 (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
903 (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
H A DX86ScheduleBtVer2.td63 def JFpuPRF: RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2], [1, 1, 0],
H A DX86ScheduleZnver1.td112 def ZnFpuPRF: RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>;
H A DX86ScheduleZnver2.td113 def Zn2FpuPRF: RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>;
H A DX86ScheduleBdVer2.td115 def PdFpuPRF : RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>;
H A DX86ScheduleZnver3.td336 def Zn3FpPRF : RegisterFile<160, [VR64, VR128, VR256], [1, 1, 1], [0, 1, 1],
H A DX86ScheduleZnver4.td333 def Zn4FpPRF : RegisterFile<192, [VR64, VR128, VR256, VR512], [1, 1, 1, 1], [0, 1, 1],
H A DX86InstrAVX512.td11539 def : Pat<(X86pinsrb VR128:$src1,
11542 (VPINSRBrr VR128:$src1, (i32 (COPY_TO_REGCLASS VK8:$src2, GR32)),
11547 def : Pat<(X86pinsrb VR128:$src1, (i32 (anyext (i8 GR8:$src2))), timm:$src3),
11548 (VPINSRBZrr VR128:$src1, (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
11550 def : Pat<(X86pinsrb VR128:$src1,
11553 (VPINSRBZrr VR128:$src1, (i32 (COPY_TO_REGCLASS VK8:$src2, GR32)),
11560 …tore f16:$src, addr:$dst), (VPEXTRWZmr addr:$dst, (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrVector.td46 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)),
47 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>;
168 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index),
169 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
170 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index),
171 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
227 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr,
229 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
230 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr,
232 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
[all …]
H A DSystemZRegisterInfo.td253 class VR128<bits<16> num, string n, FPR64 high>
261 def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,
287 defm VR128 : SystemZRegClass<"VR128",
305 def v128b : TypedReg<v16i8, VR128>;
306 def v128h : TypedReg<v8i16, VR128>;
307 def v128f : TypedReg<v4i32, VR128>;
308 def v128g : TypedReg<v2i64, VR128>;
309 def v128q : TypedReg<i128, VR128>;
310 def v128sb : TypedReg<v4f32, VR128>;
[all...]
H A DSystemZInstrFormats.td2271 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
2738 def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2742 def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2809 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
2817 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2,
2822 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2830 (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
2832 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2841 (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
2843 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
[all …]
H A DSystemZInstrFP.td26 def SelectVR128 : SelectWrapper<f128, VR128>;
91 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 VR128:$src2)))),
92 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>;
104 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 VR128:$src2)))),
105 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>;
H A DSystemZInstrInfo.td2242 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
2246 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
2247 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
2251 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
2255 (ins imm64zx48:$enc, VR128:$V1,
2259 (ins imm64zx48:$enc, VR128:$V1,
2263 (ins imm64zx48:$enc, VR128:$V1,
H A DSystemZOperands.td166 !cast<RegisterOperand>("VR128"))>;