Lines Matching refs:VR128

2271   : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
2738     def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2742       def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2809             (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
2817                         (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2,
2822                        (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2830              (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
2832              [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2841              (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
2843              [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2851             (ins VR128:$V1, (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
2853             [(operator VR128:$V1, imm32zx8:$I3, bdaddr12only:$BD2)]> {
2884     def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2889       def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
3229   : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
3247   : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
3254   : InstVRRa<opcode, (outs VR128:$V1),
3255              (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
3283     def "" : InstVRRa<opcode, (outs VR128:$V1),
3284                      (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
3287                   (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
3302   : InstVRX<opcode, (outs VR128:$V1),
3310     def Align : InstVRX<opcode, (outs VR128:$V1),
3314       def "" : InstVRX<opcode, (outs VR128:$V1),
3862   : InstVRIb<opcode, (outs VR128:$V1),
3876   : InstVRIc<opcode, (outs VR128:$V1),
3877              (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
3891   : InstVRIe<opcode, (outs VR128:$V1),
3892              (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
3896   : InstVRIh<opcode, (outs VR128:$V1),
3911   : InstVRRa<opcode, (outs VR128:$V1),
3912              (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3927   : InstVRRb<opcode, (outs VR128:$V1), (ins VR128:$V2, VR128:$V3, imm32zx4:$M5),
3933   : InstVRRb<opcode, (outs VR128:$V1),
3934              (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3951   : InstVRRb<opcode, (outs VR128:$V1),
3952              (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3980     def "" : InstVRRb<opcode, (outs VR128:$V1),
3981                      (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3984                   (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4004   : InstVRRc<opcode, (outs VR128:$V1),
4005              (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
4012   : InstVRRc<opcode, (outs VR128:$V1),
4013              (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
4033   : InstVRRc<opcode, (outs VR128:$V1),
4034              (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4045   : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
4051   : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
4065   : InstVRSa<opcode, (outs VR128:$V1),
4066              (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4:$M4),
4071   : InstVRSb<opcode, (outs VR128:$V1),
4074              [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
4091              (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4: $M4),
4096   : InstVRSd<opcode, (outs VR128:$V1),
4099              [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
4106   : InstVRX<opcode, (outs VR128:$V1),
4153   : InstVSI<opcode, (outs VR128:$V1),
4156             [(set VR128:$V1, (operator imm32zx8:$I3, bdaddr12only:$BD2))]> {
4164             (ins VR128:$V1, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4379   : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4395   : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4428   : InstVRRg<opcode, (outs), (ins VR128:$V1),
4647   : InstVRIi<opcode, (outs VR128:$V1),
4664   : InstVRRa<opcode, (outs VR128:$V1),
4665              (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
4704     def "" : InstVRRb<opcode, (outs VR128:$V1),
4705                      (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
4708                   (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4738   : InstVRRc<opcode, (outs VR128:$V1),
4739              (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4756   : InstVRRd<opcode, (outs VR128:$V1),
4757              (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
4781     def "" : InstVRRd<opcode, (outs VR128:$V1),
4782                       (ins VR128:$V2, VR128:$V3, VR128:$V4,
4786                   (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4787                                             VR128:$V4, imm32zx4:$M5, 0)>;
4806   : InstVRRe<opcode, (outs VR128:$V1),
4807              (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4824   : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2,
4829   : InstVRRj<opcode, (outs VR128:$V1), (ins VR128:$V2,
4830                                         VR128:$V3, imm32zx4:$M4),
4834   : InstVRSb<opcode, (outs VR128:$V1),
4835              (ins VR128:$V1src, GR64:$R3, (shift12only $B2, $D2):$BD2,
4844   : InstVRV<opcode, (outs VR128:$V1),
4845            (ins VR128:$V1src, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4882   : InstVRId<opcode, (outs VR128:$V1),
4883              (ins VR128:$V1src, VR128:$V2, VR128:$V3,
4891   : InstVRIf<opcode, (outs VR128:$V1),
4892              (ins VR128:$V2, VR128:$V3,
4897   : InstVRIg<opcode, (outs VR128:$V1),
4898              (ins VR128:$V2, imm32zx8:$I3,
4918   : InstVRRd<opcode, (outs VR128:$V1),
4919              (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4949                   (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4950                                             VR128:$V4, imm32zx4_timm:$M5, 0)>;
5430   : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;