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Searched refs:VMX (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrTDX.td19 // SEAMCALL - Call to SEAM VMX-root Operation Module
22 // SEAMRET - Return to Legacy VMX-root Operation
H A DX86InstrVMX.td1 //===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===//
9 // This file describes the instructions that make up the Intel VMX instruction
15 // VMX instructions
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp920 Register VMX = VMXl; in expandPostRAPseudo() local
922 VMX = VMXu; in expandPostRAPseudo()
930 .addDef(VMX) in expandPostRAPseudo()
936 .addDef(VMX) in expandPostRAPseudo()
944 .addDef(VMX) in expandPostRAPseudo()
947 .addReg(VMX); in expandPostRAPseudo()
953 .addDef(VMX) in expandPostRAPseudo()
956 .addReg(VMX); in expandPostRAPseudo()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h16 #define VMX_OFFSET(regname) (offsetof(VMX, regname) + sizeof(GPR) + sizeof(FPR))
18 (offsetof(VSX, regname) + sizeof(GPR) + sizeof(FPR) + sizeof(VMX))
391 } VMX; typedef
H A DRegisterContextFreeBSD_powerpc.cpp169 } VMX; typedef
H A DRegisterInfos_powerpc.h14 #define VMX_OFFSET(regname) (sizeof(GPR) + sizeof(FPR) + offsetof(VMX, regname))
/freebsd/sys/powerpc/conf/
H A DMPC85XXSPE63 # The powerpcspe target arch can run non Altivec/VMX powerpc binaries
/freebsd/sys/contrib/xen/arch-x86/
H A Dcpufeatureset.h130 XEN_CPUFEATURE(VMX, 1*32+ 5) /*h Virtual Machine Extensions */
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP8.td57 // Two issue ports shared by 2 DFP/2 VSX/2 VMX/1 CY/1 DFP operations.
71 // Two issue ports shared by two floating-point, two VSX, two VMX, one crypto,
H A DP10InstrResources.td1746 // 4 Cycles Permute operations, and 7 Cycles VMX Multiply operations, 2 input operands
2013 // 7 Cycles VMX Multiply operations, 2 input operands
2041 // 7 Cycles VMX Multiply operations, 3 input operands
H A DPPCInstrVSX.td15 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
23 // ** When adding new VMX and VSX instructions, please consider whether they **
1968 2. Shift in the VMX register so that the correct doubleword is correctly
1992 // - Now that we set up the shift amount, we shift in the VMX register
2025 // - Now that we set up the shift amount, we shift in the VMX register
2055 // - Now that we set up the shift amount, we shift in the VMX register
2085 // - Now that we set up the shift amount, we shift in the VMX register
2115 - The shift in the VMX register is by 0/8 for opposite element numbers so
2133 - The shift in the VMX register is by 0/8 for opposite element numbers so
2152 - The shift in the VMX register happens for opposite element numbers
[all …]
H A DPPCInstrAltivec.td15 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
23 // ** When adding new VMX and VSX instructions, please consider whether they **
1325 // instructions than VMX instructions)
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZ13.td1259 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMX(B|F|G|H)?$")>;
H A DSystemZScheduleZ14.td1280 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMX(B|F|G|H)?$")>;
H A DSystemZScheduleZ15.td1317 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMX(B|F|G|H)?$")>;
H A DSystemZScheduleZ16.td1323 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMX(B|F|G|H)?$")>;
H A DSystemZInstrVector.td581 def VMX : BinaryVRRcGeneric<"vmx", 0xE7FF>;