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Searched refs:VEX (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrSSE.td218 VEX, VVVV, VEX_LIG, WIG;
223 VEX, VEX_LIG, Sched<[WriteFStore]>, WIG;
251 VEX, VEX_LIG, Sched<[WriteFLoad]>, WIG;
262 VEX, VEX_LIG, Sched<[WriteFLoad]>, WIG;
355 TB, VEX, WIG;
358 TB, PD, VEX, WIG;
361 TB, VEX, WIG;
364 TB, PD, VEX, WIG;
368 TB, VEX, VEX_L, WIG;
371 TB, PD, VEX, VEX_L, WIG;
[all …]
H A DX86InstrAMX.td49 defm "" : AMX_TILE_COMMON<"", NoEGPR>, VEX;
55 "tilerelease", [(int_x86_tilerelease)]>, VEX, T8, PS;
58 VEX, T8, XD;
104 VEX, VVVV, T8, XD;
108 VEX, VVVV, T8, XS;
112 VEX, VVVV, T8, PD;
116 VEX, VVVV, T8;
176 []>, VEX, VVVV, T8, XS;
206 []>, VEX, VVVV, T8, XD;
235 []>, T8, PD, VEX, VVVV;
[all …]
H A DX86InstrMisc.td1218 defm BLSR32 : Bls<"blsr", MRM1r, MRM1m, Xi32>, VEX;
1219 defm BLSR64 : Bls<"blsr", MRM1r, MRM1m, Xi64>, VEX;
1220 defm BLSMSK32 : Bls<"blsmsk", MRM2r, MRM2m, Xi32>, VEX;
1221 defm BLSMSK64 : Bls<"blsmsk", MRM2r, MRM2m, Xi64>, VEX;
1222 defm BLSI32 : Bls<"blsi", MRM3r, MRM3m, Xi32>, VEX;
1223 defm BLSI64 : Bls<"blsi", MRM3r, MRM3m, Xi64>, VEX;
1302 defm BEXTR32 : Bmi4VOp3<0xF7, "bextr", Xi32, X86bextr, WriteBEXTR>, VEX;
1303 defm BEXTR64 : Bmi4VOp3<0xF7, "bextr", Xi64, X86bextr, WriteBEXTR>, VEX;
1306 defm BZHI32 : Bmi4VOp3<0xF5, "bzhi", Xi32, X86bzhi, WriteBZHI>, VEX;
1307 defm BZHI64 : Bmi4VOp3<0xF5, "bzhi", Xi64, X86bzhi, WriteBZHI>, VEX;
[all …]
H A DX86CompressEVEX.cpp284 case X86II::VEX: in CompressEVEXImpl()
H A DX86InstrPredicates.td11 // Intel x86 instructions have three separate encoding spaces: legacy, VEX, and
28 // Besides, some instructions in legacy space with map 2/3 and VEX space are
H A DX86InstrFMA3Info.cpp162 bool IsFMA3Encoding = ((TSFlags & X86II::EncodingMask) == X86II::VEX && in getFMA3Group()
H A DX86InstrFormats.td197 // Force the instruction to use REX2/VEX/EVEX encoding.
252 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field?
H A DX86InstrUtils.td43 class VEX { Encoding OpEnc = EncVEX; }
864 VEX, VVVV, FMASC, Requires<[HasFMA, NoFMA4, NoVLX]>;
868 VEX, VVVV, FMASC, Requires<[HasFMA, NoFMA4, NoAVX512]>;
872 VEX, VVVV, FMASC, Requires<[HasFMA, NoAVX512]>;
878 VEX, VVVV, FMASC, Requires<[HasFMA4, NoVLX]>;
882 VEX, VVVV, FMASC, Requires<[HasFMA4, NoAVX512]>;
886 VEX, VVVV, FMASC, Requires<[HasFMA4]>;
905 // XOP 5 operand instruction (VEX encoding!)
909 VEX, VVVV, Requires<[HasXOP]>;
H A DX86ReplaceableInstrs.def405 // Special table for changing EVEX logic instructions to VEX.
406 // TODO: Should we run EVEX->VEX earlier?
H A DX86InstrSystem.td468 T_MAP7, VEX, XD, NoCD8;
471 T_MAP7, VEX, XD, NoCD8;
481 T_MAP7, VEX, XS, NoCD8;
484 []>, T_MAP7, VEX, XS, NoCD8;
H A DX86InstrShiftRotate.td555 def ri : RorXri<t>, VEX;
556 def mi : RorXmi<t>, VEX;
586 def rr : ShiftXrr<m, t>, VEX;
587 def rm : ShiftXrm<m, t>, VEX;
H A DX86InstrArithmetic.td1385 defm ANDN32 : AndN<Xi32, X86and_flag>, VEX, Requires<[HasBMI, NoEGPR]>, DefEFLAGS;
1386 defm ANDN64 : AndN<Xi64, X86and_flag>, VEX, Requires<[HasBMI, NoEGPR]>, DefEFLAGS;
1423 (ins t.RegClass:$src), "mulx", mulx_args, []>, T8, XD, VEX,
1427 (ins t.MemOperand:$src), "mulx", mulx_args, []>, T8, XD, VEX,
H A DX86InstrAVX512.td836 // smaller extract to enable EVEX->VEX.
869 // smaller extract to enable EVEX->VEX.
2659 VEX, TB, PD;
2668 VEX, TB;
2676 VEX, TB, PD, REX_W;
2678 VEX, TB, XD;
2680 VEX, TB, REX_W;
2682 VEX, TB, XD, REX_W;
2803 sched, HasDQI>, VEX, TB, PD;
2805 sched, HasAVX512>, VEX, TB;
[all …]
H A DX86RegisterInfo.td804 // Represents the lower 16 registers that have VEX/legacy encodable subregs.
H A DX86ISelDAGToDAG.cpp1773 if ((TSFlags & X86II::EncodingMask) != X86II::VEX && in PostprocessISelDAG()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DX86EVEX2VEXTablesEmitter.cpp
H A DX86RecognizableInstr.h174 enum { VEX = 1, XOP = 2, EVEX = 3 }; enumerator
H A DX86InstrMappingEmitter.cpp203 if (RI.Encoding == X86Local::VEX) in emitCompressEVEXTable()
H A DX86RecognizableInstr.cpp325 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { in insnContext()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86EncodingOptimization.cpp39 if (!Desc.isCommutable() || (TSFlags & X86II::EncodingMask) != X86II::VEX || in optimizeInstFromVEX3ToVEX2()
H A DX86BaseInfo.h818 VEX = 1 << EncodingShift, enumerator
H A DX86MCTargetDesc.cpp540 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX; in clearsSuperRegisters()
H A DX86MCCodeEmitter.cpp996 case X86II::VEX: in emitVEXOpcodePrefix()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td1450 // Section 8.16.4 - VEX (Vector Expand)
1451 defm VEX : RV1m<"vex", 0x9d, V64, VM>;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp4252 if ((TSFlags & X86II::EncodingMask) != X86II::VEX) in checkTargetMatchPredicate()

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