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Searched refs:VECTOR_SHUFFLE (Results 1 – 25 of 33) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1257 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
1258 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
1259 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, in getShuffleCost()
1260 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, in getShuffleCost()
1261 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, in getShuffleCost()
1262 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, in getShuffleCost()
1264 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, in getShuffleCost()
1265 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, in getShuffleCost()
1266 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, in getShuffleCost()
1267 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}}; in getShuffleCost()
[all …]
H A DARMISelLowering.cpp201 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
268 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
347 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
423 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
465 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
1031 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR, in ARMTargetLowering()
10678 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG, Subtarget); in LowerOperation()
18699 N->getOperand(0).getOpcode() == ISD::VECTOR_SHUFFLE && in PerformMVETruncCombine()
18700 N->getOperand(1).getOpcode() == ISD::VECTOR_SHUFFLE) { in PerformMVETruncCombine()
18729 Op.getOpcode() == ISD::VECTOR_SHUFFLE || in PerformMVETruncCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h636 VECTOR_SHUFFLE, enumerator
H A DSelectionDAGNodes.h1690 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, VTs), Mask(M) {}
1736 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
H A DSDPatternMatch.h918 return BinaryOpc_match<V1_t, V2_t>(ISD::VECTOR_SHUFFLE, v1, v2);
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp116 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); in initializeHVXLowering()
117 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); in initializeHVXLowering()
158 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v128f16, ByteW); in initializeHVXLowering()
159 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f16, ByteV); in initializeHVXLowering()
160 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f32, ByteW); in initializeHVXLowering()
161 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v32f32, ByteV); in initializeHVXLowering()
253 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV); in initializeHVXLowering()
319 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW); in initializeHVXLowering()
3570 if (V0.getOpcode() != ISD::VECTOR_SHUFFLE) in combineConcatVectorsBeforeLegal()
3572 if (V1.getOpcode() != ISD::VECTOR_SHUFFLE) in combineConcatVectorsBeforeLegal()
H A DHexagonISelLowering.cpp1735 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE, in HexagonTargetLowering()
1853 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in HexagonTargetLowering()
1854 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in HexagonTargetLowering()
1855 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
3392 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAGHVX.cpp2814 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in ppHvxShuffleOfShuffle()
2824 if (V0.getOpcode() != ISD::VECTOR_SHUFFLE) in ppHvxShuffleOfShuffle()
2826 if (V1.getOpcode() != ISD::VECTOR_SHUFFLE) in ppHvxShuffleOfShuffle()
H A DHexagonISelDAGToDAG.cpp1024 case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N); in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp255 case ISD::VECTOR_SHUFFLE: in getIdiomaticVectorType()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp198 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in WebAssemblyTargetLowering()
235 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); in WebAssemblyTargetLowering()
238 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f16, Custom); in WebAssemblyTargetLowering()
1667 case ISD::VECTOR_SHUFFLE: in LowerOperation()
2304 if (Op.getOpcode() != ISD::VECTOR_SHUFFLE) in GetExtendHigh()
3512 case ISD::VECTOR_SHUFFLE: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp349 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; in getOperationName()
H A DDAGCombiner.cpp2022 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); in visit()
6274 if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) { in hoistLogicOpWithSameOpcodeHands()
16660 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && in visitBITCAST()
16738 N0.getOpcode() == ISD::VECTOR_SHUFFLE || in visitFREEZE()
23281 if (CurVec.getOpcode() == ISD::VECTOR_SHUFFLE && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
23730 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
23750 if (LegalOperations && TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VecVT) && in visitEXTRACT_VECTOR_ELT()
23769 TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) { in visitEXTRACT_VECTOR_ELT()
24198 !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1)) in createBuildVecShuffle()
24230 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1)) in createBuildVecShuffle()
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H A DSelectionDAG.cpp940 case ISD::VECTOR_SHUFFLE: { in AddNodeIDCustom()
2288 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, VTs, Ops); in getVectorShuffle()
3067 case ISD::VECTOR_SHUFFLE: { in isSplatValue()
3225 case ISD::VECTOR_SHUFFLE: { in getSplatSourceVector()
3490 case ISD::VECTOR_SHUFFLE: { in computeKnownBits()
4790 case ISD::VECTOR_SHUFFLE: { in ComputeNumSignBits()
5468 case ISD::VECTOR_SHUFFLE: { in isGuaranteedNotToBeUndefOrPoison()
5658 case ISD::VECTOR_SHUFFLE: { in canCreateUndefOrPoison()
8015 case ISD::VECTOR_SHUFFLE: in getNode()
H A DLegalizeVectorTypes.cpp77 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; in ScalarizeVectorResult()
1175 case ISD::VECTOR_SHUFFLE: in SplitVectorResult()
4706 case ISD::VECTOR_SHUFFLE: in WidenVectorResult()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp599 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand); in NVPTXTargetLowering()
612 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2bf16, Expand); in NVPTXTargetLowering()
623 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i16, Expand); in NVPTXTargetLowering()
628 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in NVPTXTargetLowering()
632 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f32, Expand); in NVPTXTargetLowering()
2902 case ISD::VECTOR_SHUFFLE: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp439 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in SystemZTargetLowering()
787 ISD::VECTOR_SHUFFLE, in SystemZTargetLowering()
5927 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) { in add()
6578 if (PackedOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in lowerSIGN_EXTEND_VECTOR_INREG()
7114 case ISD::VECTOR_SHUFFLE: in LowerOperation()
7552 else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) && in combineExtract()
8147 Op1.getOpcode() == ISD::VECTOR_SHUFFLE && in combineSTORE()
9037 Op.getOpcode() == ISD::VECTOR_SHUFFLE) { in detectEvenOddMultiplyOperand()
9139 case ISD::VECTOR_SHUFFLE: return combineVECTOR_SHUFFLE(N, DCI); in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp835 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); in PPCTargetLowering()
836 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
912 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
1073 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); in PPCTargetLowering()
1121 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); in PPCTargetLowering()
1427 setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE}); in PPCTargetLowering()
12605 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
16418 if (Mask[0] >= NumElts && LHS.getOpcode() != ISD::VECTOR_SHUFFLE && in combineVectorShuffle()
16419 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) { in combineVectorShuffle()
16609 Use.getUser()->getOpcode() != ISD::VECTOR_SHUFFLE) in combineVReverseMemOP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp681 case ISD::VECTOR_SHUFFLE: in Select()
3235 } else if (Src.getOpcode() == ISD::VECTOR_SHUFFLE && in SelectVOP3PMods()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1909 case ShuffleVector: return ISD::VECTOR_SHUFFLE; in InstructionOpcodeToISD()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp387 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); in addMSAIntType()
505 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFragmentsSIMD.td341 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
H A DX86ISelLowering.cpp1069 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); in X86TargetLowering()
1193 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1200 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1669 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1781 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2043 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2206 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2276 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2427 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2450 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32bf16, Custom); in X86TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp293 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in LoongArchTargetLowering()
361 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in LoongArchTargetLowering()
506 case ISD::VECTOR_SHUFFLE: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2038 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
2357 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Default); in addTypeForFixedLengthSVE()
7332 case ISD::VECTOR_SHUFFLE: in LowerOperation()
15226 SDValue VECTOR_SHUFFLE = in LowerBUILD_VECTOR() local
15228 return VECTOR_SHUFFLE; in LowerBUILD_VECTOR()
18656 BV.getOpcode() != ISD::VECTOR_SHUFFLE) in performBuildShuffleExtendCombine()
18672 if (BV.getOpcode() == ISD::VECTOR_SHUFFLE && in performBuildShuffleExtendCombine()
21267 } else if (B.getOpcode() == ISD::VECTOR_SHUFFLE) { in isLoadOrMultipleLoads()
21281 if (B.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE || in isLoadOrMultipleLoads()

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