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Searched refs:VECTOR_SHUFFLE (Results 1 – 25 of 31) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1230 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
1231 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
1232 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, in getShuffleCost()
1233 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, in getShuffleCost()
1234 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, in getShuffleCost()
1235 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, in getShuffleCost()
1237 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, in getShuffleCost()
1238 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, in getShuffleCost()
1239 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, in getShuffleCost()
1240 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}}; in getShuffleCost()
[all …]
H A DARMISelLowering.cpp196 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
263 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
342 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
413 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
455 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
1033 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR, in ARMTargetLowering()
10617 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG, Subtarget); in LowerOperation()
18628 N->getOperand(0).getOpcode() == ISD::VECTOR_SHUFFLE && in PerformMVETruncCombine()
18629 N->getOperand(1).getOpcode() == ISD::VECTOR_SHUFFLE) { in PerformMVETruncCombine()
18658 Op.getOpcode() == ISD::VECTOR_SHUFFLE || in PerformMVETruncCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h614 VECTOR_SHUFFLE, enumerator
H A DSelectionDAGNodes.h1604 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, VTs), Mask(M) {}
1649 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp116 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); in initializeHVXLowering()
117 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); in initializeHVXLowering()
156 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v128f16, ByteW); in initializeHVXLowering()
157 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f16, ByteV); in initializeHVXLowering()
158 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f32, ByteW); in initializeHVXLowering()
159 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v32f32, ByteV); in initializeHVXLowering()
249 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV); in initializeHVXLowering()
313 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW); in initializeHVXLowering()
3533 if (V0.getOpcode() != ISD::VECTOR_SHUFFLE) in combineConcatVectorsBeforeLegal()
3535 if (V1.getOpcode() != ISD::VECTOR_SHUFFLE) in combineConcatVectorsBeforeLegal()
[all...]
H A DHexagonISelLowering.cpp1665 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE, in HexagonTargetLowering()
1779 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in HexagonTargetLowering()
1780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in HexagonTargetLowering()
1781 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
3370 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAGHVX.cpp2823 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in ppHvxShuffleOfShuffle()
2833 if (V0.getOpcode() != ISD::VECTOR_SHUFFLE) in ppHvxShuffleOfShuffle()
2835 if (V1.getOpcode() != ISD::VECTOR_SHUFFLE) in ppHvxShuffleOfShuffle()
H A DHexagonISelDAGToDAG.cpp1023 case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N); in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp255 case ISD::VECTOR_SHUFFLE: in getIdiomaticVectorType()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp180 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in WebAssemblyTargetLowering()
214 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); in WebAssemblyTargetLowering()
1489 case ISD::VECTOR_SHUFFLE: in LowerOperation()
2889 case ISD::VECTOR_SHUFFLE: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp332 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; in getOperationName()
H A DDAGCombiner.cpp1959 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); in visit()
5896 if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) { in hoistLogicOpWithSameOpcodeHands()
15593 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && in visitBITCAST()
15667 N0.getOpcode() == ISD::VECTOR_SHUFFLE || in visitFREEZE()
22217 if (CurVec.getOpcode() == ISD::VECTOR_SHUFFLE && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
22687 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
22721 TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) { in visitEXTRACT_VECTOR_ELT()
23142 !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1)) in createBuildVecShuffle()
23175 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1)) in createBuildVecShuffle()
23325 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT)) in reduceBuildVecToShuffle()
[all …]
H A DSelectionDAG.cpp915 case ISD::VECTOR_SHUFFLE: { in AddNodeIDCustom()
2231 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, VTs, Ops); in getVectorShuffle()
2819 case ISD::VECTOR_SHUFFLE: { in isSplatValue()
2977 case ISD::VECTOR_SHUFFLE: { in getSplatSourceVector()
3247 case ISD::VECTOR_SHUFFLE: { in computeKnownBits()
4519 case ISD::VECTOR_SHUFFLE: { in ComputeNumSignBits()
5183 case ISD::VECTOR_SHUFFLE: { in isGuaranteedNotToBeUndefOrPoison()
5340 case ISD::VECTOR_SHUFFLE: { in canCreateUndefOrPoison()
7483 case ISD::VECTOR_SHUFFLE: in getNode()
H A DLegalizeVectorTypes.cpp75 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; in ScalarizeVectorResult()
1127 case ISD::VECTOR_SHUFFLE: in SplitVectorResult()
4345 case ISD::VECTOR_SHUFFLE: in WidenVectorResult()
6246 // Use VECTOR_SHUFFLE to combine new vector from 'ReverseVal' for in WidenVecRes_VECTOR_REVERSE()
H A DLegalizeDAG.cpp3474 case ISD::VECTOR_SHUFFLE: { in ExpandNode()
5324 case ISD::VECTOR_SHUFFLE: { in PromoteNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp496 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand); in NVPTXTargetLowering()
509 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2bf16, Expand); in NVPTXTargetLowering()
520 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i16, Expand); in NVPTXTargetLowering()
525 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in NVPTXTargetLowering()
2771 case ISD::VECTOR_SHUFFLE: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp417 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in SystemZTargetLowering()
721 ISD::VECTOR_SHUFFLE, in SystemZTargetLowering()
5340 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) { in add()
6217 case ISD::VECTOR_SHUFFLE: in LowerOperation()
6541 else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) && in combineExtract()
7081 Op1.getOpcode() == ISD::VECTOR_SHUFFLE && in combineSTORE()
7820 case ISD::VECTOR_SHUFFLE: return combineVECTOR_SHUFFLE(N, DCI); in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp826 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); in PPCTargetLowering()
827 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
903 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
1056 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); in PPCTargetLowering()
1104 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); in PPCTargetLowering()
1402 setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE}); in PPCTargetLowering()
11854 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
15536 if (Mask[0] >= NumElts && LHS.getOpcode() != ISD::VECTOR_SHUFFLE && in combineVectorShuffle()
15537 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) { in combineVectorShuffle()
15734 if (UI.getUse().getResNo() == 0 && UI->getOpcode() != ISD::VECTOR_SHUFFLE) in combineVReverseMemOP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1822 case ShuffleVector: return ISD::VECTOR_SHUFFLE; in InstructionOpcodeToISD()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp348 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); in addMSAIntType()
466 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp255 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in LoongArchTargetLowering()
302 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in LoongArchTargetLowering()
426 case ISD::VECTOR_SHUFFLE: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFragmentsSIMD.td322 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
H A DX86ISelLowering.cpp1054 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); in X86TargetLowering()
1172 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1179 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1645 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1752 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2010 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2143 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2212 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2337 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2356 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32bf16, Custom); in X86TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1869 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
2120 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Default); in addTypeForFixedLengthSVE()
6864 case ISD::VECTOR_SHUFFLE: in LowerOperation()
14332 SDValue VECTOR_SHUFFLE = in LowerBUILD_VECTOR() local
14334 return VECTOR_SHUFFLE; in LowerBUILD_VECTOR()
18088 BV.getOpcode() != ISD::VECTOR_SHUFFLE) in performBuildShuffleExtendCombine()
18103 if (BV.getOpcode() == ISD::VECTOR_SHUFFLE && in performBuildShuffleExtendCombine()
20526 } else if (B.getOpcode() == ISD::VECTOR_SHUFFLE) { in isLoadOrMultipleLoads()
20540 if (B.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE || in isLoadOrMultipleLoads()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp519 ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
539 ISD::FCOPYSIGN, ISD::VECTOR_SHUFFLE, ISD::SETCC, in AMDGPUTargetLowering()

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