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/freebsd/crypto/openssl/crypto/sm3/asm/
H A Dsm3-riscv64-zvksh.pl67 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
82 @{[vle32_v $V0, $CTX]}
83 @{[vrev8_v $V0, $V0]}
88 @{[vmv_v_v $V2, $V0]}
104 @{[vsm3c_vi $V0, $V6, 0]}
105 @{[vsm3c_vi $V0, $V4, 1]}
111 @{[vsm3c_vi $V0, $V4, 2]}
113 @{[vsm3c_vi $V0, $V4, 3]}
115 @{[vsm3c_vi $V0, $V8, 4]}
117 @{[vsm3c_vi $V0, $V4, 5]}
[all …]
/freebsd/crypto/openssl/crypto/modes/asm/
H A Dghash-riscv64-zvkb-zvbc.pl69 my ($V0,$V1,$V2,$V3,$V4,$V5,$V6) = ("v0","v1","v2","v3","v4","v5","v6");
100 @{[vmv_v_i $V0, 2]} # vmv.v.i v0, 2
104 @{[vmv_v_v $V0, $V3]} # vmv.v.v v0, v3
107 @{[vmv_v_v $V0, $V3]} # vmv.v.v v0, v3
125 my ($V0,$V1,$V2,$V3,$V4,$V5,$V6) = ("v0","v1","v2","v3","v4","v5","v6");
177 @{[vmv_v_i $V0, 1]} # vmv.v.i v0, 1
183 @{[vmv_v_i $V0, 2]} # vmv.v.i v0, 2
219 @{[vmv_v_i $V0, 1]} # vmv.v.i v0, 1
246 my ($V0,$V1,$V2,$V3,$V4,$V5,$V6,$Vinp) = ("v0","v1","v2","v3","v4","v5","v6","v7");
307 @{[vmv_v_i $V0, 1]} # vmv.v.i v0, 1
[all …]
H A Dghash-riscv64-zvkg.pl90 my ($Htable,$H,$V0) = ("a0","a1","v0");
98 @{[vle64_v $V0, $H]} # vle64.v v0, (a1)
99 @{[vrev8_v $V0, $V0]} # vrev8.v v0, v0
100 @{[vse64_v $V0, $Htable]} # vse64.v v0, (a0)
H A Daes-gcm-riscv64-zvkb-zvkg-zvkned.pl89 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
587 @{[vmv_v_v $V0, $V20]}
588 @{[vgmul_vv $V0, $V1]}
595 @{[vghsh_vv $V0, $V1, $V4]}
680 @{[vse32_v $V0, $XIP]}
729 @{[vse32_v $V0, $XIP]}
778 @{[vse32_v $V0, $XIP]}
864 @{[vse32_v $V0, $XIP]}
913 @{[vse32_v $V0, $XIP]}
962 @{[vse32_v $V0, $XIP]}
/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha256-riscv64-zvkb-zvknha_or_zvknhb.pl63 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
147 @{[vmv_v_i $V0, 0x01]}
178 @{[vmerge_vvm $V5, $V3, $V2, $V0]}
185 @{[vmerge_vvm $V5, $V4, $V3, $V0]}
192 @{[vmerge_vvm $V5, $V1, $V4, $V0]}
199 @{[vmerge_vvm $V5, $V2, $V1, $V0]}
206 @{[vmerge_vvm $V5, $V3, $V2, $V0]}
213 @{[vmerge_vvm $V5, $V4, $V3, $V0]}
220 @{[vmerge_vvm $V5, $V1, $V4, $V0]}
227 @{[vmerge_vvm $V5, $V2, $V1, $V0]}
[all …]
H A Dsha512-riscv64-zvkb-zvknhb.pl63 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
106 @{[vmv_v_i $V0, 0x01]}
143 @{[vmerge_vvm $V18, $V14, $V12, $V0]}
152 @{[vmerge_vvm $V18, $V16, $V14, $V0]}
161 @{[vmerge_vvm $V18, $V10, $V16, $V0]}
170 @{[vmerge_vvm $V18, $V12, $V10, $V0]}
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp84 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
95 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) in initGlobalBaseReg()
97 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) in initGlobalBaseReg()
109 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
111 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg()
124 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
126 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
148 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure in initGlobalBaseReg()
151 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
152 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
83 Register V0 = RegInfo.createVirtualRegister(RC); initGlobalBaseReg() local
[all...]
H A DMips16ISelDAGToDAG.cpp66 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF); in initGlobalBaseReg() local
69 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
74 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0) in initGlobalBaseReg()
79 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16); in initGlobalBaseReg()
H A DMipsRegisterInfo.td90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
125 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
288 V0, V1, A0, A1, A2, A3,
308 V0, V1, A0, A1, A2, A3,
324 V0, V1, A0, A1, A2, A3)>;
332 V0, V1, A0, A1, A2, A3)>;
340 V0, V1,
370 V0, V1, A0, A1, A2, A3,
376 V0, V1, A0, A1, A2, A3,
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp66 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
73 if (R >= Hexagon::V0 && R <= Hexagon::V31) { in getStringReg()
78 return S[R-Hexagon::V0]; in getStringReg()
175 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { in runOnMachineFunction()
176 LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n'); in runOnMachineFunction()
180 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, in runOnMachineFunction()
182 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, in runOnMachineFunction()
H A DHexagonCallingConv.td127 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
149 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
167 CCAssignToReg<[V0]>>>,
175 CCAssignToReg<[V0]>>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVMV0Elimination.cpp97 assert(!(MI.readsRegister(RISCV::V0, TRI) && V0Clobbered) && in runOnMachineFunction()
99 if (MI.modifiesRegister(RISCV::V0, TRI)) in runOnMachineFunction()
108 [](auto *Succ) { return Succ->isLiveIn(RISCV::V0); })) && in runOnMachineFunction()
139 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::COPY), RISCV::V0) in runOnMachineFunction()
142 MO.setReg(RISCV::V0); in runOnMachineFunction()
H A DRISCVVectorMaskDAGMutation.cpp43 return MI.isFullCopy() && MI.getOperand(0).getReg() == RISCV::V0 && in isCopyToV0()
72 if (MI->findRegisterUseOperand(RISCV::V0, TRI)) in apply()
/freebsd/crypto/openssl/crypto/chacha/asm/
H A Dchacha-riscv64-v-zbb.pl92 $V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7, $V8, $V9, $V10,
278 # init chacha const states into $V0~$V3
281 @{[vmv_v_x $V0, $CONST_DATA0]}
328 # - $V0~$V15 for chacha states.
338 $V0, $V4, $V8, $V12,
349 $V0, $V5, $V10, $V15,
369 @{[vadd_vx $V0, $V0, $T0]}
397 @{[vxor_vv $V16, $V16, $V0]}
434 @{[vid_v $V0]}
444 @{[vadd_vv $V12, $V12, $V0]}
/freebsd/lib/msun/src/
H A De_j1.c130 static const double V0[5] = { variable
188 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4])))); in y1()
H A De_j1f.c93 static const float V0[5] = { variable
144 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4])))); in y1f()
/freebsd/crypto/openssl/crypto/aes/asm/
H A Daes-riscv64-zvbb-zvkg-zvkned.pl76 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
120 @{[vbrev8_v $V0, $V28]}
124 @{[vaesz_vs $V16, $V0]}
161 @{[vmv_v_i $V0, 0]}
163 @{[vmv_v_x $V0, $T0]}
165 @{[vbrev8_v $V0, $V0]}
168 @{[vaesz_vs $V20, $V0]}
/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/
H A DVecUtils.h176 Value *V0 = Bndl[0];
177 Type *Ty0 = Utils::getExpectedType(V0);
192 Value *V0 = Bndl[0];
193 Type *Ty0 = Utils::getExpectedType(V0);
H A DLegality.h283 auto *V0 = Descr0.getValue(); in getSingleInput() local
289 if (Descr.getValue() != V0) in getSingleInput()
293 return std::make_pair(V0, ShuffleMask(std::move(MaskIndices))); in getSingleInput()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp47 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
198 SDValue V0 = N->getOperand(i + 1); in selectInlineAsm() local
200 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in selectInlineAsm()
383 SDNode *CSKYDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode() argument
384 SDLoc dl(V0.getNode()); in createGPRPairNode()
389 const SDValue Ops[] = {RegClass, V0, SubReg0, V1, SubReg1}; in createGPRPairNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECallingConv.td107 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
110 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
128 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
131 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp328 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
329 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
330 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
331 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
334 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
335 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
336 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1844 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode() argument
1845 SDLoc dl(V0.getNode()); in createGPRPairNode()
1850 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
[all …]
/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DDarwin.h544 bool isIPhoneOSVersionLT(unsigned V0, unsigned V1 = 0,
547 return TargetVersion < VersionTuple(V0, V1, V2);
554 bool isMacosxVersionLT(unsigned V0, unsigned V1 = 0, unsigned V2 = 0) const {
565 : TargetVersion) < VersionTuple(V0, V1, V2);
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVectorCombine.cpp584 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); in foldExtExtCmp() local
585 Value *VecCmp = Builder.CreateCmp(Pred, V0, V1); in foldExtExtCmp()
602 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); in foldExtExtBinop() local
604 Builder.CreateBinOp(cast<BinaryOperator>(&I)->getOpcode(), V0, V1); in foldExtExtBinop()
628 Value *V0, *V1; in foldExtractExtract() local
630 if (!match(I0, m_ExtractElt(m_Value(V0), m_ConstantInt(C0))) || in foldExtractExtract()
632 V0->getType() != V1->getType()) in foldExtractExtract()
876 Value *V0, *V1; in foldBitcastShuffle() local
879 m_Shuffle(m_Value(V0), m_Value(V1), m_Mask(Mask)))))) in foldBitcastShuffle()
888 auto *SrcTy = dyn_cast<FixedVectorType>(V0->getType()); in foldBitcastShuffle()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp283 MCRegister Reg = RISCV::V0 + RegNo; in DecodeVRRegisterClass()
298 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM2RegisterClass()
315 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM4RegisterClass()
332 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM8RegisterClass()
345 Inst.addOperand(MCOperand::createReg(RISCV::V0)); in DecodeVMV0RegisterClass()
388 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister; in decodeVMaskReg()

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