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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVVLPatterns.td642 (mask_type V0),
651 (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
669 (mask_type V0),
676 (mask_type V0),
698 (mask_type V0),
707 (mask_type V0),
761 (mask_type V0),
766 (mask_type V0), GPR:$vl, sew, TU_MU)>;
830 (mask_type V0),
839 (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
[all …]
H A DRISCVInstrInfoZvk.td695 (vti.Mask V0),
700 (vti.Mask V0),
715 (vti.Mask V0),
719 (vti.Mask V0),
725 (vti.Mask V0),
734 (vti.Mask V0),
740 (vti.Mask V0),
762 (vti.Mask V0), VLOpFrag),
767 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
782 (vti.Mask V0), VLOpFrag),
[all …]
H A DRISCVVectorPeephole.cpp133 MaskDef->getOperand(0).getReg() == RISCV::V0); in isAllOnesMask()
185 assert(MI.getOperand(4).isReg() && MI.getOperand(4).getReg() == RISCV::V0); in convertVMergeToVMv()
272 if (MI.readsRegister(RISCV::V0, TRI)) in runOnMachineFunction()
275 if (MI.definesRegister(RISCV::V0, TRI)) in runOnMachineFunction()
H A DRISCVInstrInfoVSDPatterns.td975 …def : Pat<(shl (wti.Vector (riscv_sext_vl_oneuse (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), VL…
979 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
980 …def : Pat<(shl (wti.Vector (riscv_zext_vl_oneuse (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), VL…
984 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
1128 def : Pat<(vti.Vector (vselect (vti.Mask V0), vti.RegClass:$rs1,
1132 vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0),
1135 def : Pat<(vti.Vector (vselect (vti.Mask V0), (SplatPat XLenVT:$rs1),
1139 vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), vti.AVL, vti.Log2SEW)>;
1141 def : Pat<(vti.Vector (vselect (vti.Mask V0), (SplatPat_simm5 simm5:$rs1),
1145 vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), vti.AVL, vti.Log2SEW)>;
[all …]
H A DRISCVInstrInfoVPseudos.td1184 // Mask can be V0~V31
1414 // Like VPseudoBinaryMaskPolicy, but output can be V0 and there is no policy.
3997 (mask_type V0),
4005 (mask_type V0), GPR:$vl, log2sew, (XLenVT timm:$policy))>;
4021 (mask_type V0),
4030 (mask_type V0),
4048 (mask_type V0),
4057 (mask_type V0),
4076 (mti.Mask V0),
4081 (mti.Mask V0), GP
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp84 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
95 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) in initGlobalBaseReg()
97 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) in initGlobalBaseReg()
109 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
111 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg()
124 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
126 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
148 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure in initGlobalBaseReg()
151 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
152 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
83 Register V0 = RegInfo.createVirtualRegister(RC); initGlobalBaseReg() local
[all...]
H A DMips16ISelDAGToDAG.cpp75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF); in initGlobalBaseReg() local
78 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0) in initGlobalBaseReg()
88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16); in initGlobalBaseReg()
H A DMipsRegisterInfo.td90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
125 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
288 V0, V1, A0, A1, A2, A3,
308 V0, V1, A0, A1, A2, A3,
324 V0, V1, A0, A1, A2, A3)>;
332 V0, V1, A0, A1, A2, A3)>;
340 V0, V1,
370 V0, V1, A0, A1, A2, A3,
376 V0, V1, A0, A1, A2, A3,
H A DMipsCallingConv.td99 // i32 are returned in registers V0, V1, A0, A1, unless the original return
102 CCAssignToReg<[V0, V1, A0, A1]>>>,
269 // except for AT, V0 and T9, are available to be used as argument registers.
315 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
385 CalleeSavedRegs<(add V0, V1, FP,
H A DMipsBranchExpansion.cpp736 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0) in emitGPDisp()
738 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0) in emitGPDisp()
739 .addReg(Mips::V0) in emitGPDisp()
741 MBB.removeLiveIn(Mips::V0); in emitGPDisp()
H A DMipsAsmPrinter.cpp924 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0); in EmitSwapFPIntRetval()
927 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
930 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
933 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
81 if (R >= Hexagon::V0 && R <= Hexagon::V31) { in getStringReg()
86 return S[R-Hexagon::V0]; in getStringReg()
183 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { in runOnMachineFunction()
184 LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n'); in runOnMachineFunction()
188 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, in runOnMachineFunction()
190 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, in runOnMachineFunction()
H A DHexagonCallingConv.td116 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
130 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
148 CCAssignToReg<[V0]>>>,
156 CCAssignToReg<[V0]>>>,
H A DHexagonISelDAGToDAG.cpp2315 SDValue V0 = L0.Value; in balanceSubTree() local
2321 if ((RootWeights.count(V0.getNode()) && RootWeights[V0.getNode()] == -2) || in balanceSubTree()
2327 ConstantSDNode *V0C = dyn_cast<ConstantSDNode>(V0); in balanceSubTree()
2333 std::swap(V0, V1); in balanceSubTree()
2338 assert(NodeHeights.count(V0) && NodeHeights.count(V1) && in balanceSubTree()
2340 int Height = std::max(NodeHeights[V0], NodeHeights[V1]) + 1; in balanceSubTree()
2345 ISD::SHL, SDLoc(V0), VT, V0, in balanceSubTree()
2348 TLI.getScalarShiftAmountTy(DL, V0.getValueType()))); in balanceSubTree()
2350 NewNode = CurDAG->getNode(NOpcode, SDLoc(N), VT, V0, V1); in balanceSubTree()
2373 SDValue V0 = NewRoot.getOperand(0); in balanceSubTree() local
[all …]
/freebsd/lib/msun/src/
H A De_j1.c130 static const double V0[5] = { variable
188 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4])))); in y1()
H A De_j1f.c93 static const float V0[5] = { variable
144 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4])))); in y1f()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVectorCombine.cpp542 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); in foldExtExtCmp() local
543 Value *VecCmp = Builder.CreateCmp(Pred, V0, V1); in foldExtExtCmp()
560 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); in foldExtExtBinop() local
562 Builder.CreateBinOp(cast<BinaryOperator>(&I)->getOpcode(), V0, V1); in foldExtExtBinop()
586 Value *V0, *V1; in foldExtractExtract() local
588 if (!match(I0, m_ExtractElt(m_Value(V0), m_ConstantInt(C0))) || in foldExtractExtract()
590 V0->getType() != V1->getType()) in foldExtractExtract()
698 Value *V0, *V1; in foldBitcastShuffle() local
701 m_Shuffle(m_Value(V0), m_Value(V1), m_Mask(Mask)))))) in foldBitcastShuffle()
710 auto *SrcTy = dyn_cast<FixedVectorType>(V0->getType()); in foldBitcastShuffle()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp47 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
198 SDValue V0 = N->getOperand(i + 1); in selectInlineAsm() local
200 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in selectInlineAsm()
383 SDNode *CSKYDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode() argument
384 SDLoc dl(V0.getNode()); in createGPRPairNode()
389 const SDValue Ops[] = {RegClass, V0, SubReg0, V1, SubReg1}; in createGPRPairNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECallingConv.td107 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
110 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
128 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
131 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DDarwin.h497 bool isIPhoneOSVersionLT(unsigned V0, unsigned V1 = 0,
500 return TargetVersion < VersionTuple(V0, V1, V2);
507 bool isMacosxVersionLT(unsigned V0, unsigned V1 = 0, unsigned V2 = 0) const {
518 : TargetVersion) < VersionTuple(V0, V1, V2);
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp209 MCRegister Reg = RISCV::V0 + RegNo; in DecodeVRRegisterClass()
224 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM2RegisterClass()
241 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM4RegisterClass()
258 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM8RegisterClass()
271 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister; in decodeVMaskReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp337 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
338 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
339 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
340 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
343 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
344 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
345 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1853 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode() argument
1854 SDLoc dl(V0.getNode()); in createGPRPairNode()
1859 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp84 Value *V0, *V1; in cheapToScalarize() local
85 if (match(V, m_OneUse(m_BinOp(m_Value(V0), m_Value(V1))))) in cheapToScalarize()
86 if (cheapToScalarize(V0, EI) || cheapToScalarize(V1, EI)) in cheapToScalarize()
90 if (match(V, m_OneUse(m_Cmp(UnusedPred, m_Value(V0), m_Value(V1))))) in cheapToScalarize()
91 if (cheapToScalarize(V0, EI) || cheapToScalarize(V1, EI)) in cheapToScalarize()
2055 Value *V0 = nullptr, Value *V1 = nullptr) : in BinopElts()
2056 Opcode(Opc), Op0(V0), Op1(V1) {} in BinopElts()
2609 Value *V0 = Shuf.getOperand(0), *V1 = Shuf.getOperand(1); in foldShuffleWithInsert() local
2614 int InpNumElts = cast<FixedVectorType>(V0->getType())->getNumElements(); in foldShuffleWithInsert()
2623 if (match(V0, m_InsertElt(m_Value(X), m_Value(), m_ConstantInt(IdxC)))) { in foldShuffleWithInsert()
[all …]
H A DInstCombineAddSub.cpp391 Value *V0 = I->getOperand(0); in drillValueDownOneStep() local
393 if (ConstantFP *C = dyn_cast<ConstantFP>(V0)) { in drillValueDownOneStep()
399 Addend0.set(C, V0); in drillValueDownOneStep()
469 Value *V0 = I->getOperand(0); in simplify() local
471 InstQuota = ((!isa<Constant>(V0) && V0->hasOneUse()) && in simplify()
2284 Value *V0, *V1; in visitSub() local
2285 if (match(Op0, m_AddRdx(V0)) && match(Op1, m_AddRdx(V1)) && in visitSub()
2286 V0->getType() == V1->getType()) { in visitSub()
2289 Value *Sub = Builder.CreateSub(V0, V1); in visitSub()
2967 Value *A0, *A1, *V0, *V1; in visitFSub() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp232 SDValue V0 = N->getOperand(i+1); in tryInlineAsm() local
234 Register Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm()

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