337   SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
338   SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
339   SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
340   SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
343   SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
344   SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
345   SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1853 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {  in createGPRPairNode()  argument
1854   SDLoc dl(V0.getNode());  in createGPRPairNode()
1859   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createGPRPairNode()
1864 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {  in createSRegPairNode()  argument
1865   SDLoc dl(V0.getNode());  in createSRegPairNode()
1870   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createSRegPairNode()
1875 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {  in createDRegPairNode()  argument
1876   SDLoc dl(V0.getNode());  in createDRegPairNode()
1881   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createDRegPairNode()
1886 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {  in createQRegPairNode()  argument
1887   SDLoc dl(V0.getNode());  in createQRegPairNode()
1892   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createQRegPairNode()
1897 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,  in createQuadSRegsNode()  argument
1899   SDLoc dl(V0.getNode());  in createQuadSRegsNode()
1906   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in createQuadSRegsNode()
1912 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,  in createQuadDRegsNode()  argument
1914   SDLoc dl(V0.getNode());  in createQuadDRegsNode()
1921   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in createQuadDRegsNode()
1927 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,  in createQuadQRegsNode()  argument
1929   SDLoc dl(V0.getNode());  in createQuadQRegsNode()
1936   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in createQuadQRegsNode()
2318       SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVST()  local
2321         SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);  in SelectVST()
2329         SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVST()
2374   SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVST()  local
2380   SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);  in SelectVST()
2493   SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVLDSTLane()  local
2497       SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);  in SelectVLDSTLane()
2499       SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);  in SelectVLDSTLane()
2506       SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVLDSTLane()
2508       SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);  in SelectVLDSTLane()
5780     SDValue V0 = N->getOperand(i+1);  in tryInlineAsm()  local
5782     Register Reg0 = cast<RegisterSDNode>(V0)->getReg();  in tryInlineAsm()