| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VERegisterInfo.cpp | 296 Register TmpReg = VE::SX16; in processSTVM() local
298 build(VE::SVMmr, TmpReg).addReg(SrcReg).addImm(i); in processSTVM()
301 TmpReg, getKillRegState(true)); in processSTVM()
305 build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3); in processSTVM()
307 MI.getOperand(3).ChangeToRegister(TmpReg, false, false, true); in processSTVM()
333 unsigned TmpReg = VE::SX16; in processLDVM() local
337 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0); in processLDVM()
343 MI.getOperand(0).ChangeToRegister(TmpReg, true); in processLDVM()
348 build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true)); in processLDVM()
352 .addReg(TmpReg, getKillRegState(true)) in processLDVM()
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| H A D | VEInstrInfo.cpp | 375 Register TmpReg = VE::SX16; in copyPhysReg() local
376 Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32); in copyPhysReg()
377 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg) in copyPhysReg()
385 MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true); in copyPhysReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 325 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect() local
326 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) in selectI64ImmDirect()
331 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
342 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect() local
343 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) in selectI64ImmDirect()
348 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
373 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect() local
374 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) in selectI64ImmDirect()
379 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
401 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SpeculationHardening.cpp | 156 unsigned TmpReg) const;
304 Register TmpReg = RS.FindUnusedReg(&AArch64::GPR64commonRegClass); in instrumentControlFlow() local
306 << ((TmpReg == 0) ? "no register " : "register "); in instrumentControlFlow()
307 if (TmpReg != 0) dbgs() << printReg(TmpReg, TRI) << " "; in instrumentControlFlow()
309 if (TmpReg == 0) in instrumentControlFlow()
312 ReturnInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow()
314 CallInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow()
381 unsigned TmpReg) const { in insertRegToSPTaintPropagation()
390 .addDef(TmpReg) in insertRegToSPTaintPropagation()
396 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2745 MCRegister TmpReg = DstReg; in loadImmediate() local
2753 TmpReg = ATReg; in loadImmediate()
2773 MCRegister TmpReg = DstReg; in loadImmediate() local
2775 TmpReg = getATReg(IDLoc); in loadImmediate()
2776 if (!TmpReg) in loadImmediate()
2780 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2782 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2795 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate()
2796 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
2798 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb1InstrInfo.cpp | 82 Register TmpReg = ARM::NoRegister; in copyPhysReg() local
85 TmpReg = ARM::R12; in copyPhysReg()
89 TmpReg = Reg; in copyPhysReg()
95 if (TmpReg) { in copyPhysReg()
96 BuildMI(MBB, I, DL, get(ARM::tMOVr), TmpReg) in copyPhysReg()
100 .addReg(TmpReg, getKillRegState(true)) in copyPhysReg()
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| H A D | ThumbRegisterInfo.cpp | 602 Register TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
606 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex()
609 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex()
615 BuildMI(MBB, II, dl, TII.get(ARM::tADDhirr), TmpReg) in eliminateFrameIndex()
616 .addReg(TmpReg) in eliminateFrameIndex()
622 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex()
627 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
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| H A D | MLxExpansionPass.cpp | 287 Register TmpReg = in ExpandFPMLxInstruction() local
290 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction()
302 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
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| H A D | Thumb1FrameLowering.cpp | 586 unsigned &TmpReg, MachineRegisterInfo &MRI) { in findTemporariesForLR() argument
587 PopReg = TmpReg = 0; in findTemporariesForLR()
593 TmpReg = 0; in findTemporariesForLR()
598 TmpReg = Reg; in findTemporariesForLR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 146 Register TmpReg = createResultReg(ToRC); in copyRegToRegClass() local
148 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg); in copyRegToRegClass()
149 return TmpReg; in copyRegToRegClass()
1010 Register TmpReg = createResultReg(&PPC::G8RCRegClass); in PPCMoveToFPReg() local
1011 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) in PPCMoveToFPReg()
1013 SrcReg = TmpReg; in PPCMoveToFPReg()
1105 Register TmpReg = createResultReg(&PPC::G8RCRegClass); in SelectIToFP() local
1106 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned)) in SelectIToFP()
1109 SrcReg = TmpReg; in SelectIToFP()
1431 Register TmpReg = createResultReg(RC); in processCallArgs() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/ |
| H A D | LoongArchAsmParser.cpp | 131 void emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg,
866 void LoongArchAsmParser::emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg, in emitLAInstSeq() argument
909 .addReg(DestReg == TmpReg ? DestReg : TmpReg) in emitLAInstSeq()
910 .addReg(DestReg == TmpReg ? DestReg : TmpReg) in emitLAInstSeq()
916 MCInstBuilder(Opc).addReg(TmpReg).addReg(TmpReg).addExpr(LE), in emitLAInstSeq()
922 .addReg(TmpReg) in emitLAInstSeq()
923 .addReg(DestReg == TmpReg ? TmpReg : LoongArch::R0) in emitLAInstSeq()
930 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addReg(TmpReg), in emitLAInstSeq()
1004 MCRegister TmpReg = Inst.getOperand(1).getReg(); in emitLoadAddressPcrelLarge() local
1018 emitLAInstSeq(DestReg, TmpReg, Symbol, Insts, IDLoc, Out); in emitLoadAddressPcrelLarge()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaFrameLowering.cpp | 73 MCRegister TmpReg = Xtensa::A8; in emitPrologue() local
78 TII.loadImmediate(MBB, MBBI, &TmpReg, StackSize - MIN_FRAME_SIZE); in emitPrologue()
79 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::SUB), TmpReg) in emitPrologue()
81 .addReg(TmpReg); in emitPrologue()
82 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::MOVSP), SP).addReg(TmpReg); in emitPrologue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 1063 Register TmpReg = i < NumInsts - 1 in materializeImm() local
1072 Result = MIB.buildInstr(I.getOpcode(), {TmpReg}, {}) in materializeImm()
1077 Result = MIB.buildInstr(I.getOpcode(), {TmpReg}, in materializeImm()
1081 Result = MIB.buildInstr(I.getOpcode(), {TmpReg}, {SrcReg, SrcReg}); in materializeImm()
1085 MIB.buildInstr(I.getOpcode(), {TmpReg}, {SrcReg}).addImm(I.getImm()); in materializeImm()
1092 SrcReg = TmpReg; in materializeImm()
1302 Register TmpReg = DstReg; in selectFPCompare() local
1308 TmpReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); in selectFPCompare()
1309 auto Cmp = MIB.buildInstr(getFCmpOpcode(Pred, Size), {TmpReg}, {LHS, RHS}); in selectFPCompare()
1324 TmpReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); in selectFPCompare()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 1523 Register TmpReg = MRI->createVirtualRegister(PS->RC); in mergePredStateIntoSP() local
1527 auto ShiftI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHL64ri), TmpReg) in mergePredStateIntoSP()
1534 .addReg(TmpReg, RegState::Kill); in mergePredStateIntoSP()
1544 Register TmpReg = MRI->createVirtualRegister(PS->RC); in extractPredStateFromSP() local
1549 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), TmpReg) in extractPredStateFromSP()
1553 .addReg(TmpReg, RegState::Kill) in extractPredStateFromSP()
1651 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() local
1686 TII->get(Is128Bit ? X86::VPORrr : X86::VPORYrr), TmpReg) in hardenLoadAddr()
1717 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOp), TmpReg) in hardenLoadAddr()
1730 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), TmpReg) in hardenLoadAddr()
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| H A D | X86CmovConversion.cpp | 772 Register TmpReg = MRI->createVirtualRegister(RC); in convertCmovInstsToBranches() local
777 bool Unfolded = TII->unfoldMemoryOperand(*MBB->getParent(), MI, TmpReg, in convertCmovInstsToBranches()
821 FalseBBRegRewriteTable[NewCMOV->getOperand(0).getReg()] = TmpReg; in convertCmovInstsToBranches()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 333 Register TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local
336 TmpReg) in foldVGPRCopyIntoRegSequence()
346 .addReg(TmpReg, RegState::Kill); in foldVGPRCopyIntoRegSequence()
347 TmpReg = TmpAReg; in foldVGPRCopyIntoRegSequence()
350 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence()
894 Register TmpReg = in lowerSpecialCase() local
897 TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg) in lowerSpecialCase()
899 MI.getOperand(1).setReg(TmpReg); in lowerSpecialCase()
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| H A D | SIRegisterInfo.cpp | 2823 Register TmpReg; in eliminateFrameIndex() local
2828 TmpReg = DstOp.getReg(); in eliminateFrameIndex()
2834 if (!TmpReg) in eliminateFrameIndex()
2835 TmpReg = RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass, in eliminateFrameIndex()
2838 if (TmpReg) { in eliminateFrameIndex()
2840 .addDef(TmpReg, RegState::Renamable) in eliminateFrameIndex()
2845 MaterializedReg = TmpReg; in eliminateFrameIndex()
2865 if (!TmpReg && MaterializedReg == FrameReg) { in eliminateFrameIndex()
2866 TmpReg = RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass, in eliminateFrameIndex()
2869 DstReg = TmpReg; in eliminateFrameIndex()
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| H A D | SILowerI1Copies.cpp | 625 Register TmpReg = createLaneMaskReg(MRI, LaneMaskRegAttrs); in lowerCopiesToI1() local
626 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg) in lowerCopiesToI1()
629 MI.getOperand(1).setReg(TmpReg); in lowerCopiesToI1()
630 SrcReg = TmpReg; in lowerCopiesToI1()
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| H A D | SIWholeQuadMode.cpp | 939 Register TmpReg; in lowerKillI1() local
966 TmpReg = MRI->createVirtualRegister(TRI->getBoolRC()); in lowerKillI1()
968 BuildMI(MBB, MI, DL, TII->get(AndN2Opc), TmpReg).addReg(Exec).add(Op); in lowerKillI1()
971 .addReg(TmpReg); in lowerKillI1()
1032 if (TmpReg) in lowerKillI1()
1033 LIS->createAndComputeVirtRegInterval(TmpReg); in lowerKillI1()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 212 Register TmpReg = I->getParent()->getOperand(0).getReg(); in processCandidate() local
213 processDstReg(MRI, TmpReg, DstReg, GVal, false, IsAma); in processCandidate()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 1192 Register TmpReg = MRI.createGenericVirtualRegister(MergeEltTy); in tryCombineUnmergeValues() local
1193 Builder.buildInstr(ConvertOp, {TmpReg}, in tryCombineUnmergeValues()
1195 Builder.buildUnmerge(DstRegs, TmpReg); in tryCombineUnmergeValues()
1557 Register TmpReg = getSrcRegIgnoringCopies(Reg, MRI); in lookThroughCopyInstrs() local
1558 return TmpReg.isValid() ? TmpReg : Reg; in lookThroughCopyInstrs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 365 MCRegister TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI) { in emitLoadWithImmOffset() argument
387 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI); in emitLoadWithImmOffset()
389 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset()
391 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI); in emitLoadWithImmOffset()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 733 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local
742 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
747 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); in expandCvtFPInt()
748 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); in expandCvtFPInt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 442 MCRegister BaseReg, IndexReg, TmpReg; member in __anonee973c6c0111::X86AsmParser::IntelExprStateMachine
696 BaseReg = TmpReg; in onPlus()
700 IndexReg = TmpReg; in onPlus()
755 BaseReg = TmpReg; in onMinus()
759 IndexReg = TmpReg; in onMinus()
810 TmpReg = Reg; in onRegister()
900 IndexReg = TmpReg; in onInteger()
1000 BaseReg = TmpReg; in onRBrac()
1004 IndexReg = TmpReg; in onRBrac()
1065 BaseReg = TmpReg; in onRParen()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 138 void emitAuipcInstPair(MCRegister DestReg, MCRegister TmpReg,
3456 void RISCVAsmParser::emitAuipcInstPair(MCRegister DestReg, MCRegister TmpReg, in emitAuipcInstPair() argument
3471 MCInstBuilder(RISCV::AUIPC).addReg(TmpReg).addExpr(SymbolHi)); in emitAuipcInstPair()
3478 .addReg(TmpReg) in emitAuipcInstPair()
3568 MCRegister TmpReg = Inst.getOperand(0).getReg(); in emitLoadStoreSymbol() local
3571 if (RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(TmpReg)) { in emitLoadStoreSymbol()
3573 TmpReg = RI->getSubReg(TmpReg, RISCV::sub_gpr_even); in emitLoadStoreSymbol()
3577 emitAuipcInstPair(DestReg, TmpReg, Symbol, ELF::R_RISCV_PCREL_HI20, Opcode, in emitLoadStoreSymbol()
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