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Searched refs:TmpReg (Results 1 – 25 of 49) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp300 Register TmpReg = VE::SX16; in processSTVM() local
302 build(VE::SVMmr, TmpReg).addReg(SrcReg).addImm(i); in processSTVM()
305 TmpReg, getKillRegState(true)); in processSTVM()
309 build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3); in processSTVM()
311 MI.getOperand(3).ChangeToRegister(TmpReg, false, false, true); in processSTVM()
337 unsigned TmpReg = VE::SX16; in processLDVM() local
341 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0); in processLDVM()
347 MI.getOperand(0).ChangeToRegister(TmpReg, true); in processLDVM()
352 build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true)); in processLDVM()
356 .addReg(TmpReg, getKillRegState(true)) in processLDVM()
[all …]
H A DVEInstrInfo.cpp376 Register TmpReg = VE::SX16; in copyPhysReg() local
377 Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32); in copyPhysReg()
378 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg) in copyPhysReg()
386 MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true); in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp325 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect() local
326 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) in selectI64ImmDirect()
331 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
342 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect() local
343 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) in selectI64ImmDirect()
348 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
373 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect() local
374 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) in selectI64ImmDirect()
379 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
401 Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); in selectI64ImmDirect() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp161 unsigned TmpReg) const;
309 Register TmpReg = RS.FindUnusedReg(&AArch64::GPR64commonRegClass); in instrumentControlFlow() local
311 << ((TmpReg == 0) ? "no register " : "register "); in instrumentControlFlow()
312 if (TmpReg != 0) dbgs() << printReg(TmpReg, TRI) << " "; in instrumentControlFlow()
314 if (TmpReg == 0) in instrumentControlFlow()
317 ReturnInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow()
319 CallInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow()
386 unsigned TmpReg) const { in insertRegToSPTaintPropagation()
395 .addDef(TmpReg) in insertRegToSPTaintPropagation()
[all...]
H A DAArch64PointerAuth.cpp249 Register AuthenticatedReg, Register TmpReg, bool UseIKey, unsigned BrkImm) { in checkAuthenticatedRegister() argument
272 BuildMI(MBB, MBBI, DL, TII->get(AArch64::LDRWui), getWRegFromXReg(TmpReg)) in checkAuthenticatedRegister()
294 BuildMI(MBB, MBBI, DL, TII->get(AArch64::EORXrs), TmpReg) in checkAuthenticatedRegister()
299 .addReg(TmpReg) in checkAuthenticatedRegister()
307 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ORRXrs), TmpReg) in checkAuthenticatedRegister()
313 .addReg(TmpReg) in checkAuthenticatedRegister()
379 Register TmpReg = in checkAuthenticatedLR() local
381 assert(!TI->readsRegister(TmpReg, TRI) && in checkAuthenticatedLR()
384 checkAuthenticatedRegister(TI, Method, AArch64::LR, TmpReg, /*UseIKey=*/true, in checkAuthenticatedLR()
H A DAArch64PointerAuth.h103 Register AuthenticatedReg, Register TmpReg,
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2789 unsigned TmpReg = DstReg; in loadImmediate() local
2797 TmpReg = ATReg; in loadImmediate()
2817 unsigned TmpReg = DstReg; in loadImmediate() local
2819 TmpReg = getATReg(IDLoc); in loadImmediate()
2820 if (!TmpReg) in loadImmediate()
2824 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2826 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2839 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate()
2840 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
2842 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp81 Register TmpReg = ARM::NoRegister; in copyPhysReg() local
84 TmpReg = ARM::R12; in copyPhysReg()
88 TmpReg = Reg; in copyPhysReg()
94 if (TmpReg) { in copyPhysReg()
95 BuildMI(MBB, I, DL, get(ARM::tMOVr), TmpReg) in copyPhysReg()
99 .addReg(TmpReg, getKillRegState(true)) in copyPhysReg()
H A DThumbRegisterInfo.cpp604 Register TmpReg = MI.getOperand(0).getReg();
608 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in useFPForScavengingIndex()
611 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in useFPForScavengingIndex()
617 BuildMI(MBB, II, dl, TII.get(ARM::tADDhirr), TmpReg)
618 .addReg(TmpReg)
624 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
629 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
526 Register TmpReg = MI.getOperand(0).getReg(); eliminateFrameIndex() local
H A DMLxExpansionPass.cpp287 Register TmpReg = in ExpandFPMLxInstruction() local
290 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction()
302 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
H A DThumb1FrameLowering.cpp615 unsigned &TmpReg, MachineRegisterInfo &MRI) { in findTemporariesForLR() argument
616 PopReg = TmpReg = 0; in findTemporariesForLR()
622 TmpReg = 0; in findTemporariesForLR()
627 TmpReg = Reg; in findTemporariesForLR()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp86 void emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg,
824 void LoongArchAsmParser::emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg, in emitLAInstSeq() argument
867 .addReg(DestReg == TmpReg ? DestReg : TmpReg) in emitLAInstSeq()
868 .addReg(DestReg == TmpReg ? DestReg : TmpReg) in emitLAInstSeq()
874 MCInstBuilder(Opc).addReg(TmpReg).addReg(TmpReg).addExpr(LE), in emitLAInstSeq()
880 .addReg(TmpReg) in emitLAInstSeq()
881 .addReg(DestReg == TmpReg ? TmpReg : LoongArch::R0) in emitLAInstSeq()
888 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addReg(TmpReg), in emitLAInstSeq()
962 MCRegister TmpReg = Inst.getOperand(1).getReg(); in emitLoadAddressPcrelLarge() local
976 emitLAInstSeq(DestReg, TmpReg, Symbol, Insts, IDLoc, Out); in emitLoadAddressPcrelLarge()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp152 Register TmpReg = createResultReg(ToRC); in copyRegToRegClass() local
154 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg); in copyRegToRegClass()
155 return TmpReg; in copyRegToRegClass()
1022 Register TmpReg = createResultReg(&PPC::G8RCRegClass); in PPCMoveToFPReg() local
1023 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) in PPCMoveToFPReg()
1025 SrcReg = TmpReg; in PPCMoveToFPReg()
1117 Register TmpReg = createResultReg(&PPC::G8RCRegClass); in SelectIToFP() local
1118 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned)) in SelectIToFP()
1121 SrcReg = TmpReg; in SelectIToFP()
1442 Register TmpReg = createResultReg(RC); in processCallArgs() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp948 Register TmpReg = i < NumInsts - 1 in materializeImm() local
957 Result = MIB.buildInstr(I.getOpcode(), {TmpReg}, {}) in materializeImm()
962 Result = MIB.buildInstr(I.getOpcode(), {TmpReg}, in materializeImm()
966 Result = MIB.buildInstr(I.getOpcode(), {TmpReg}, {SrcReg, SrcReg}); in materializeImm()
970 MIB.buildInstr(I.getOpcode(), {TmpReg}, {SrcReg}).addImm(I.getImm()); in materializeImm()
977 SrcReg = TmpReg; in materializeImm()
1214 Register TmpReg = DstReg; in selectFPCompare() local
1220 TmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectFPCompare()
1221 auto Cmp = MIB.buildInstr(getFCmpOpcode(Pred, Size), {TmpReg}, {LHS, RHS}); in selectFPCompare()
1236 TmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectFPCompare()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp1526 Register TmpReg = MRI->createVirtualRegister(PS->RC); in mergePredStateIntoSP() local
1530 auto ShiftI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHL64ri), TmpReg) in mergePredStateIntoSP()
1537 .addReg(TmpReg, RegState::Kill); in mergePredStateIntoSP()
1547 Register TmpReg = MRI->createVirtualRegister(PS->RC); in extractPredStateFromSP() local
1552 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), TmpReg) in extractPredStateFromSP()
1556 .addReg(TmpReg, RegState::Kill) in extractPredStateFromSP()
1654 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() local
1689 TII->get(Is128Bit ? X86::VPORrr : X86::VPORYrr), TmpReg) in hardenLoadAddr()
1720 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOp), TmpReg) in hardenLoadAddr()
1733 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), TmpReg) in hardenLoadAddr()
[all …]
H A DX86CmovConversion.cpp775 Register TmpReg = MRI->createVirtualRegister(RC); in convertCmovInstsToBranches() local
780 bool Unfolded = TII->unfoldMemoryOperand(*MBB->getParent(), MI, TmpReg, in convertCmovInstsToBranches()
824 FalseBBRegRewriteTable[NewCMOV->getOperand(0).getReg()] = TmpReg; in convertCmovInstsToBranches()
H A DX86FlagsCopyLowering.cpp831 Register TmpReg = MRI->createVirtualRegister(PromoteRC); in rewriteArithmetic() local
835 .addDef(TmpReg, RegState::Dead) in rewriteArithmetic()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp319 Register TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local
322 TmpReg) in foldVGPRCopyIntoRegSequence()
332 .addReg(TmpReg, RegState::Kill); in foldVGPRCopyIntoRegSequence()
333 TmpReg = TmpAReg; in foldVGPRCopyIntoRegSequence()
336 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence()
878 Register TmpReg = in lowerSpecialCase() local
881 TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg) in lowerSpecialCase()
883 MI.getOperand(1).setReg(TmpReg); in lowerSpecialCase()
H A DSILowerI1Copies.cpp694 Register TmpReg = createLaneMaskReg(MRI, LaneMaskRegAttrs); in lowerCopiesToI1() local
695 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg) in lowerCopiesToI1()
698 MI.getOperand(1).setReg(TmpReg); in lowerCopiesToI1()
699 SrcReg = TmpReg; in lowerCopiesToI1()
H A DSIWholeQuadMode.cpp929 Register TmpReg; in lowerKillI1() local
956 TmpReg = MRI->createVirtualRegister(TRI->getBoolRC()); in lowerKillI1()
958 BuildMI(MBB, MI, DL, TII->get(XorOpc), TmpReg).add(Op).addReg(Exec); in lowerKillI1()
961 .addReg(TmpReg); in lowerKillI1()
1022 if (TmpReg) in lowerKillI1()
1023 LIS->createAndComputeVirtRegInterval(TmpReg); in lowerKillI1()
H A DSIRegisterInfo.cpp2356 Register TmpReg = in eliminateFrameIndex() local
2358 FIOp.setReg(TmpReg); in eliminateFrameIndex()
2361 if ((!FrameReg || !Offset) && TmpReg) { in eliminateFrameIndex()
2363 auto MIB = BuildMI(*MBB, MI, DL, TII->get(Opc), TmpReg); in eliminateFrameIndex()
2376 UseSGPR ? TmpReg in eliminateFrameIndex()
2382 if ((!TmpSReg && !FrameReg) || (!TmpReg && !UseSGPR)) in eliminateFrameIndex()
2410 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
2592 Register TmpReg = RS->scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, in eliminateFrameIndex() local
2594 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
2596 FIOp.ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp210 Register TmpReg = I->getParent()->getOperand(0).getReg(); in processCandidate() local
211 processDstReg(MRI, TmpReg, DstReg, GVal, false, IsAma); in processCandidate()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp353 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithImmOffset() argument
376 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI); in emitLoadWithImmOffset()
378 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset()
380 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI); in emitLoadWithImmOffset()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h1179 Register TmpReg = MRI.createGenericVirtualRegister(MergeEltTy); in tryCombineUnmergeValues() local
1180 Builder.buildInstr(ConvertOp, {TmpReg}, in tryCombineUnmergeValues()
1182 Builder.buildUnmerge(DstRegs, TmpReg); in tryCombineUnmergeValues()
1538 Register TmpReg = getSrcRegIgnoringCopies(Reg, MRI); in lookThroughCopyInstrs() local
1539 return TmpReg.isValid() ? TmpReg : Reg; in lookThroughCopyInstrs()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp733 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local
742 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
747 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); in expandCvtFPInt()
748 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); in expandCvtFPInt()

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