| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 87 const TargetRegisterClass *RC) const;
129 const TargetRegisterClass *
130 getLargestLegalSuperClass(const TargetRegisterClass *RC,
162 const TargetRegisterClass *getPointerRegClass(
169 const TargetRegisterClass *
170 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
172 const TargetRegisterClass *
213 const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) const;
216 const TargetRegisterClass *getAGPRClassForBitWidth(unsigned BitWidth) const;
219 const TargetRegisterClass *
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| H A D | AMDGPURewriteAGPRCopyMFMA.cpp | 63 const TargetRegisterClass *
64 recomputeRegClassExcept(Register Reg, const TargetRegisterClass *OldRC,
65 const TargetRegisterClass *NewRC,
71 const TargetRegisterClass *
73 Register Reg, const TargetRegisterClass *OldRC, in recomputeRegClassExcept()
74 const TargetRegisterClass *NewRC, const MachineInstr *ExceptMI) const { in recomputeRegClassExcept()
111 const TargetRegisterClass *VirtRegRC = MRI.getRegClass(VReg); in run()
115 const TargetRegisterClass *AssignedRC = TRI.getPhysRegBaseClass(PhysReg); in run()
176 const TargetRegisterClass *Src2VirtRegRC = in run()
185 const TargetRegisterClass *Src2ExceptRC = recomputeRegClassExcept( in run()
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| H A D | GCNRewritePartialRegUses.cpp | 66 const TargetRegisterClass *getMinSizeReg(const TargetRegisterClass *RC,
82 const TargetRegisterClass *
83 getRegClassWithShiftedSubregs(const TargetRegisterClass *RC, unsigned RShift,
107 const uint32_t *getSuperRegClassMask(const TargetRegisterClass *RC,
111 mutable SmallDenseMap<std::pair<const TargetRegisterClass *, unsigned>,
174 const TargetRegisterClass *RC, unsigned SubRegIdx) const { in getSuperRegClassMask()
205 const TargetRegisterClass *
207 const TargetRegisterClass *RC, unsigned RShift, unsigned CoverSubregIdx, in getRegClassWithShiftedSubregs()
256 const TargetRegisterClass *MinRC = nullptr; in getRegClassWithShiftedSubregs()
279 const TargetRegisterClass *
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 45 class TargetRegisterClass {
126 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
138 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
239 using regclass_iterator = const TargetRegisterClass * const *;
296 TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
302 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
308 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
313 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
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| H A D | RegisterClassInfo.h | 78 LLVM_ABI void compute(const TargetRegisterClass *RC) const;
81 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
99 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
106 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
116 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
136 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
144 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
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| H A D | LiveStacks.h | 33 class TargetRegisterClass; variable
48 std::map<int, const TargetRegisterClass *> S2RCMap;
61 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
79 const TargetRegisterClass *getIntervalRegClass(int Slot) const { in getIntervalRegClass()
81 std::map<int, const TargetRegisterClass *>::const_iterator I = in getIntervalRegClass()
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| H A D | RegisterScavenging.h | 31 class TargetRegisterClass; variable
105 BitVector getRegsAvailable(const TargetRegisterClass *RC);
109 Register FindUnusedReg(const TargetRegisterClass *RC) const; in forward()
141 Register scavengeRegisterBackwards(const TargetRegisterClass &RC,
158 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj, in getScavengingFrameIndices()
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| H A D | FastISel.h | 57 class TargetRegisterClass; variable
389 const TargetRegisterClass *RC);
394 const TargetRegisterClass *RC, Register Op0);
399 const TargetRegisterClass *RC, Register Op0,
405 const TargetRegisterClass *RC, Register Op0,
411 const TargetRegisterClass *RC, Register Op0,
417 const TargetRegisterClass *RC, Register Op0,
423 const TargetRegisterClass *RC,
429 const TargetRegisterClass *RC, Register Op0,
435 const TargetRegisterClass *RC, uint64_t Imm);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.h | 64 const TargetRegisterClass *
65 getMatchingSuperRegClass(const TargetRegisterClass *A,
66 const TargetRegisterClass *B,
69 const TargetRegisterClass *
70 getSubClassWithSubReg(const TargetRegisterClass *RC,
73 const TargetRegisterClass *
74 getLargestLegalSuperClass(const TargetRegisterClass *RC,
79 const TargetRegisterClass *
86 const TargetRegisterClass *
87 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 190 const TargetRegisterClass *
191 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { in getAllocatableClass()
197 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass()
205 static const TargetRegisterClass *
220 const TargetRegisterClass *BestRC = nullptr; in getMinimalPhysRegClass()
221 for (const TargetRegisterClass *RC : TRI->regclasses()) { in getMinimalPhysRegClass()
233 static const TargetRegisterClass *
249 const TargetRegisterClass *BestRC = nullptr; in getCommonMinimalPhysRegClass()
250 for (const TargetRegisterClass *RC : TRI->regclasses()) { in getCommonMinimalPhysRegClass()
261 const TargetRegisterClass *
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| H A D | CriticalAntiDepBreaker.cpp | 71 Classes[Reg.id()] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
89 Classes[Reg.id()] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
119 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
126 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
187 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction()
197 Classes[Reg.id()] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
206 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
207 Classes[Reg.id()] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
212 if (Classes[Reg.id()] != reinterpret_cast<TargetRegisterClass *>(-1)) in PrescanInstruction()
240 Classes[Reg.id()] == reinterpret_cast<TargetRegisterClass *>(-1)) { in PrescanInstruction()
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| H A D | MachineRegisterInfo.cpp | 58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass()
68 static const TargetRegisterClass *
70 const TargetRegisterClass *OldRC, in constrainRegClass()
71 const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass()
74 const TargetRegisterClass *NewRC = in constrainRegClass()
84 const TargetRegisterClass *MachineRegisterInfo::constrainRegClass( in constrainRegClass()
85 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass()
105 else if (isa<const TargetRegisterClass *>(RegCB) != in constrainRegAttrs()
106 isa<const TargetRegisterClass *>(ConstrainingRegCB)) in constrainRegAttrs()
108 else if (isa<const TargetRegisterClass *>(RegCB)) { in constrainRegAttrs()
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| H A D | RegisterBank.cpp | 26 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in RegisterBank()
37 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
52 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in verify()
92 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
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| H A D | RegisterCoalescer.h | 23 class TargetRegisterClass; variable
58 const TargetRegisterClass *NewRC = nullptr;
110 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 93 const TargetRegisterClass *
96 const TargetRegisterClass *
97 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
99 const TargetRegisterClass *
100 getLargestLegalSuperClass(const TargetRegisterClass *RC,
103 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
155 const TargetRegisterClass *SrcRC,
157 const TargetRegisterClass *DstRC,
159 const TargetRegisterClass *NewRC,
162 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| H A D | ThumbRegisterInfo.h | 29 const TargetRegisterClass *
30 getLargestLegalSuperClass(const TargetRegisterClass *RC,
33 const TargetRegisterClass *
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kRegisterInfo.h | 60 const TargetRegisterClass *
69 const TargetRegisterClass *RC) const;
74 const TargetRegisterClass *getMaximalPhysRegClass(unsigned reg, MVT VT) const;
77 int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const;
101 const TargetRegisterClass *
102 getCrossCopyRegClass(const TargetRegisterClass *RC) const override { in getCrossCopyRegClass()
112 const TargetRegisterClass *intRegClass(unsigned Size) const;
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| H A D | M68kRegisterInfo.cpp | 70 const TargetRegisterClass *
77 const TargetRegisterClass *RC) const { in getMatchingMegaReg()
84 const TargetRegisterClass *
91 const TargetRegisterClass *BestRC = nullptr; in getMaximalPhysRegClass()
94 const TargetRegisterClass *RC = *I; in getMaximalPhysRegClass()
107 const TargetRegisterClass &TRC) const { in getRegisterOrder()
267 const TargetRegisterClass *M68kRegisterInfo::intRegClass(unsigned size) const { in intRegClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 23 class TargetRegisterClass; variable
64 const TargetRegisterClass *
65 getSubClassWithSubReg(const TargetRegisterClass *RC,
104 const TargetRegisterClass *
107 const TargetRegisterClass *
108 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
136 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
148 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
149 unsigned SubReg, const TargetRegisterClass *DstRC,
150 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.h | 35 const TargetRegisterClass *
36 getLargestLegalSuperClass(const TargetRegisterClass *RC,
46 const TargetRegisterClass *
54 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
55 unsigned SubReg, const TargetRegisterClass *DstRC,
56 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 59 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
61 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
68 unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
72 const TargetRegisterClass *RC) const;
74 const TargetRegisterClass *
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| H A D | HexagonVLIWPacketizer.h | 25 class TargetRegisterClass; variable
123 const TargetRegisterClass *RC);
126 const TargetRegisterClass *RC);
131 const TargetRegisterClass *RC);
134 const TargetRegisterClass *RC);
146 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.h | 125 const TargetRegisterClass *
131 const TargetRegisterClass *
132 getLargestLegalSuperClass(const TargetRegisterClass *RC,
140 float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const override;
147 static bool isVRRegClass(const TargetRegisterClass *RC) { in isVRRegClass()
152 static bool isVRNRegClass(const TargetRegisterClass *RC) { in isVRNRegClass()
156 static bool isRVVRegClass(const TargetRegisterClass *RC) { in isRVVRegClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.h | 137 const TargetRegisterClass *
146 const TargetRegisterClass *
147 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
172 const TargetRegisterClass *SrcRC,
174 const TargetRegisterClass *DstRC,
176 const TargetRegisterClass *NewRC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterInfo.h | 25 class TargetRegisterClass; variable
47 const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
50 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
71 virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
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