10b57cec5SDimitry Andric //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file contains the Hexagon implementation of the TargetRegisterInfo 100b57cec5SDimitry Andric // class. 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H 150b57cec5SDimitry Andric #define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h" 180b57cec5SDimitry Andric 190b57cec5SDimitry Andric #define GET_REGINFO_HEADER 200b57cec5SDimitry Andric #include "HexagonGenRegisterInfo.inc" 210b57cec5SDimitry Andric 220b57cec5SDimitry Andric namespace llvm { 230b57cec5SDimitry Andric 240b57cec5SDimitry Andric namespace Hexagon { 250b57cec5SDimitry Andric // Generic (pseudo) subreg indices for use with getHexagonSubRegIndex. 260b57cec5SDimitry Andric enum { ps_sub_lo = 0, ps_sub_hi = 1 }; 270b57cec5SDimitry Andric } 280b57cec5SDimitry Andric 290b57cec5SDimitry Andric class HexagonRegisterInfo : public HexagonGenRegisterInfo { 300b57cec5SDimitry Andric public: 310b57cec5SDimitry Andric HexagonRegisterInfo(unsigned HwMode); 320b57cec5SDimitry Andric 330b57cec5SDimitry Andric /// Code Generation virtual methods... 340b57cec5SDimitry Andric const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) 350b57cec5SDimitry Andric const override; 360b57cec5SDimitry Andric const uint32_t *getCallPreservedMask(const MachineFunction &MF, 370b57cec5SDimitry Andric CallingConv::ID) const override; 380b57cec5SDimitry Andric 390b57cec5SDimitry Andric BitVector getReservedRegs(const MachineFunction &MF) const override; 400b57cec5SDimitry Andric 41*bdd1243dSDimitry Andric bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 420b57cec5SDimitry Andric unsigned FIOperandNum, RegScavenger *RS = nullptr) const override; 430b57cec5SDimitry Andric 440b57cec5SDimitry Andric /// Returns true since we may need scavenging for a temporary register 450b57cec5SDimitry Andric /// when generating hardware loop instructions. requiresRegisterScavenging(const MachineFunction & MF)460b57cec5SDimitry Andric bool requiresRegisterScavenging(const MachineFunction &MF) const override { 470b57cec5SDimitry Andric return true; 480b57cec5SDimitry Andric } 490b57cec5SDimitry Andric 500b57cec5SDimitry Andric /// Returns true. Spill code for predicate registers might need an extra 510b57cec5SDimitry Andric /// register. requiresFrameIndexScavenging(const MachineFunction & MF)520b57cec5SDimitry Andric bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { 530b57cec5SDimitry Andric return true; 540b57cec5SDimitry Andric } 550b57cec5SDimitry Andric 560b57cec5SDimitry Andric /// Returns true if the frame pointer is valid. 570b57cec5SDimitry Andric bool useFPForScavengingIndex(const MachineFunction &MF) const override; 580b57cec5SDimitry Andric 590b57cec5SDimitry Andric bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, 600b57cec5SDimitry Andric unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, 610b57cec5SDimitry Andric const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override; 620b57cec5SDimitry Andric 630b57cec5SDimitry Andric // Debug information queries. 640b57cec5SDimitry Andric Register getFrameRegister(const MachineFunction &MF) const override; 65*bdd1243dSDimitry Andric Register getFrameRegister() const; 66*bdd1243dSDimitry Andric Register getStackRegister() const; 670b57cec5SDimitry Andric 680b57cec5SDimitry Andric unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC, 690b57cec5SDimitry Andric unsigned GenIdx) const; 700b57cec5SDimitry Andric 710b57cec5SDimitry Andric const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF, 720b57cec5SDimitry Andric const TargetRegisterClass *RC) const; 730b57cec5SDimitry Andric 740b57cec5SDimitry Andric const TargetRegisterClass * 750b57cec5SDimitry Andric getPointerRegClass(const MachineFunction &MF, 760b57cec5SDimitry Andric unsigned Kind = 0) const override; 770b57cec5SDimitry Andric 78*bdd1243dSDimitry Andric bool isEHReturnCalleeSaveReg(Register Reg) const; 790b57cec5SDimitry Andric }; 800b57cec5SDimitry Andric 810b57cec5SDimitry Andric } // end namespace llvm 820b57cec5SDimitry Andric 830b57cec5SDimitry Andric #endif 84