Searched refs:TBL (Results 1 – 12 of 12) sorted by relevance
/freebsd/usr.bin/column/ |
H A D | column.c | 208 } TBL; typedef 214 TBL *t; in maketbl() 218 TBL *tbl; in maketbl() 222 if ((t = tbl = calloc(entries, sizeof(TBL))) == NULL) in maketbl()
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/freebsd/usr.bin/man/ |
H A D | man.sh | 409 local EQN NROFF PIC TBL TROFF REFER VGRIND 447 for tool in EQN NROFF PIC TBL TROFF REFER VGRIND; do 473 t) pipeline="$pipeline | $TBL" ;; 481 pipeline="$TBL" 1094 TBL=tbl
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/freebsd/contrib/bmake/mk/ |
H A D | doc.mk | 20 TBL?= tbl
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/freebsd/share/mk/ |
H A D | bsd.doc.mk | 60 TBL?= tbl
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 349 TBL, enumerator
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H A D | AArch64SchedFalkorDetails.td | 957 def : InstRW<[FalkorWr_3VXVY_5cyc], (instregex "^TBL(v8i8Three|v16i8Two)$")>; 960 def : InstRW<[FalkorWr_4VXVY_6cyc], (instregex "^TBL(v8i8Four|v16i8Three)$")>;
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H A D | AArch64SchedOryon.td | 1579 // TBL 1-reg/2-reg; TBX 1-reg, 1uOp, throughput=4 latency=2 1584 // TBL 3-reg/4-reg, 3uops, throughtput=4/3=1.33 latency=4
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H A D | AArch64SchedCyclone.td | 611 // TBL,TBX are WriteV.
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H A D | AArch64ISelLowering.cpp | 2694 MAKE_CASE(AArch64ISD::TBL) in getTargetNodeName() 5762 return DAG.getNode(AArch64ISD::TBL, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN() 13382 SDValue TBL = DAG.getNode(AArch64ISD::TBL, DL, MVT::nxv2i64, V, ShuffleMask); in LowerDUPQLane() local 13383 return DAG.getNode(ISD::BITCAST, DL, VT, TBL); in LowerDUPQLane()
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H A D | AArch64InstrInfo.td | 933 def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>; 6567 // AdvSIMD TBL/TBX instructions 6570 defm TBL : SIMDTableLookup< 0, "tbl">;
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H A D | AArch64InstrFormats.td | 8093 // AdvSIMD TBL/TBX
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/freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
H A D | arm_sve.td | 1040 // Note: svdup_lane is implemented using the intrinsic for TBL to represent a
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