Subtarget (reference) in projects: freebsd

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Searched refs:Subtarget (Results 1 – 25 of 312) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A D	X86InstrPredicates.td	35 def HasEGPR : Predicate<"Subtarget->hasEGPR()">; 36 def NoEGPR : Predicate<"!Subtarget->hasEGPR()">; 46 def HasNDD : Predicate<"Subtarget->hasNDD()">; 47 def NoNDD : Predicate<"!Subtarget->hasNDD()">; 48 def HasCF : Predicate<"Subtarget->hasCF()">; 49 def HasCMOV : Predicate<"Subtarget->canUseCMOV()">; 50 def NoCMOV : Predicate<"!Subtarget->canUseCMOV()">; 51 def HasNOPL : Predicate<"Subtarget->hasNOPL()">; 52 def HasMMX : Predicate<"Subtarget->hasMMX()">; 53 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; [all …]
H A D	X86ISelLoweringCall.cpp	71 const X86Subtarget &Subtarget) { in handleMaskRegisterForCallingConv() argument 86 if (NumElts == 32 && (!Subtarget.hasBWI() \|\| CC != CallingConv::X86_RegCall)) in handleMaskRegisterForCallingConv() 89 if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) { in handleMaskRegisterForCallingConv() 90 if (Subtarget.useAVX512Regs()) in handleMaskRegisterForCallingConv() 96 if (!isPowerOf2_32(NumElts) \|\| (NumElts == 64 && !Subtarget.hasBWI()) \|\| in handleMaskRegisterForCallingConv() 107 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) { in getRegisterTypeForCallingConv() 113 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget); in getRegisterTypeForCallingConv() 123 if ((VT == MVT::f64 \|\| VT == MVT::f80) && !Subtarget.is64Bit() && in getRegisterTypeForCallingConv() 124 !Subtarget.hasX87()) in getRegisterTypeForCallingConv() 141 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) { in getNumRegistersForCallingConv() [all …]
H A D	X86SelectionDAGInfo.cpp	62 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset() local 69 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemset() 88 if (Subtarget.is64Bit() && Alignment >= Align(8)) { // QWORD aligned in EmitTargetCodeForMemset() 121 bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in EmitTargetCodeForMemset() 156 static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepmovs() argument 159 const bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in emitRepmovs() 178 static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepmovsB() argument 181 return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitRepmovsB() 186 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget, in getOptimalRepmovsType() argument 199 return Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in getOptimalRepmovsType() [all …]
H A D	X86ISelLowering.cpp	129 : TargetLowering(TM), Subtarget(STI) { in X86TargetLowering() 130 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87(); in X86TargetLowering() 147 if (Subtarget.isAtom()) in X86TargetLowering() 149 else if (Subtarget.is64Bit()) in X86TargetLowering() 153 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in X86TargetLowering() 158 if (Subtarget.hasSlowDivide32()) in X86TargetLowering() 160 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit()) in X86TargetLowering() 165 if (Subtarget.isTargetWindowsMSVC() \|\| Subtarget.isTargetWindowsItanium()) { in X86TargetLowering() 184 if (Subtarget.canUseCMPXCHG16B()) in X86TargetLowering() 186 else if (Subtarget.canUseCMPXCHG8B()) in X86TargetLowering() [all …]
H A D	X86FastISel.cpp	50 const X86Subtarget *Subtarget; member in __anonec6fb4fc0111::X86FastISel 56 Subtarget = &funcInfo.MF->getSubtarget<X86Subtarget>(); in X86FastISel() 130 return Subtarget->getInstrInfo(); in getInstrInfo() 150 return (VT == MVT::f64 && Subtarget->hasSSE2()) \|\| in isScalarFPTypeInSSEReg() 151 (VT == MVT::f32 && Subtarget->hasSSE1()) \|\| VT == MVT::f16; in isScalarFPTypeInSSEReg() 299 if (VT == MVT::f64 && !Subtarget->hasSSE2()) in isTypeLegal() 301 if (VT == MVT::f32 && !Subtarget->hasSSE1()) in isTypeLegal() 319 bool HasSSE1 = Subtarget->hasSSE1(); in X86FastEmitLoad() 320 bool HasSSE2 = Subtarget->hasSSE2(); in X86FastEmitLoad() 321 bool HasSSE41 = Subtarget->hasSSE41(); in X86FastEmitLoad() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A D	ARMPredicates.td	9 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 11 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 12 def HasV5T : Predicate<"Subtarget->hasV5TOps()">, 14 def NoV5T : Predicate<"!Subtarget->hasV5TOps()">; 15 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 17 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 19 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 20 def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 23 def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">, 26 def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, [all …]
H A D	ARMMachineFunctionInfo.cpp	`30 const ARMSubtarget Subtarget) { in GetBranchTargetEnforcement() argument 31 if (!Subtarget->isMClass() \|\| !Subtarget->hasV7Ops()) in GetBranchTargetEnforcement() 56 const ARMSubtarget Subtarget) in ARMFunctionInfo() argument 57 : isThumb(Subtarget->isThumb()), hasThumb2(Subtarget->hasThumb2()), in ARMFunctionInfo() 60 BranchTargetEnforcement(GetBranchTargetEnforcement(F, Subtarget)) { in ARMFunctionInfo() 61 if (Subtarget->isMClass() && Subtarget->hasV7Ops()) in ARMFunctionInfo()`
H A D	ARMSelectionDAGInfo.cpp	41 const ARMSubtarget &Subtarget = in EmitSpecializedLibcall() local 43 const ARMTargetLowering *TLI = Subtarget.getTargetLowering(); in EmitSpecializedLibcall() 141 static bool shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget, in shouldGenerateInlineTPLoop() argument 161 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold() && in shouldGenerateInlineTPLoop() 163 Subtarget.getMaxMemcpyTPInlineSizeThreshold()) in shouldGenerateInlineTPLoop() 172 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemcpy() local 176 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemcpy() 177 shouldGenerateInlineTPLoop(Subtarget, DAG, ConstantSize, Alignment, true)) in EmitTargetCodeForMemcpy() 191 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy() 202 const unsigned MaxLoadsInLDM = Subtarget.isThumb1Only() ? 4 : 6; in EmitTargetCodeForMemcpy() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A D	MipsRegisterInfo.cpp	94 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>(); in getCalleeSavedRegs() local 97 if (Subtarget.hasMips64()) in getCalleeSavedRegs() 98 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList in getCalleeSavedRegs() 101 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList in getCalleeSavedRegs() 105 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs() 108 if (Subtarget.isABI_N64()) in getCalleeSavedRegs() 111 if (Subtarget.isABI_N32()) in getCalleeSavedRegs() 114 if (Subtarget.isFP64bit()) in getCalleeSavedRegs() 117 if (Subtarget.isFPXX()) in getCalleeSavedRegs() 126 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); in getCallPreservedMask() local [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A D	AMDGPU.td	23 // Subtarget Features (device properties) 963 // Subtarget Features (options and debugging) 1768 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">, 1772 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS \|\|" 1773 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">, 1777 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS \|\|" 1778 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS \|\|" 1779 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">, 1783 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS \|\|" 1784 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS \|\|" [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A D	PPCLowerMASSVEntries.cpp	54 static StringRef getCPUSuffix(const PPCSubtarget Subtarget); 56 const PPCSubtarget Subtarget); 59 const PPCSubtarget Subtarget); 75 StringRef PPCLowerMASSVEntries::getCPUSuffix(const PPCSubtarget Subtarget) { in getCPUSuffix() argument 77 if (!Subtarget) in getCPUSuffix() 80 if (Subtarget->isAIXABI() && Subtarget->hasP10Vector()) in getCPUSuffix() 82 if (Subtarget->hasP9Vector()) in getCPUSuffix() 84 if (Subtarget->hasP8Vector()) in getCPUSuffix() 86 if (Subtarget->isAIXABI()) in getCPUSuffix() 98 const PPCSubtarget *Subtarget) { in createMASSVFuncName() argument [all …]
H A D	PPCRegisterInfo.cpp	186 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); in getCalleeSavedRegs() local 188 if (!TM.isPPC64() && Subtarget.isAIXABI()) in getCalleeSavedRegs() 190 if (Subtarget.hasVSX()) { in getCalleeSavedRegs() 191 if (Subtarget.pairedVectorMemops()) in getCalleeSavedRegs() 193 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) in getCalleeSavedRegs() 197 if (Subtarget.hasAltivec()) { in getCalleeSavedRegs() 198 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) in getCalleeSavedRegs() 213 !Subtarget.isUsingPCRelativeCalls(); in getCalleeSavedRegs() 217 if (Subtarget.isAIXABI()) in getCalleeSavedRegs() 220 if (Subtarget.pairedVectorMemops()) in getCalleeSavedRegs() [all …]
H A D	PPCFrameLowering.cpp	85 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering() 86 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), in PPCFrameLowering() 87 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), in PPCFrameLowering() 88 LinkageSize(computeLinkageSize(Subtarget)), in PPCFrameLowering() 89 BasePointerSaveOffset(computeBasePointerSaveOffset(Subtarget)), in PPCFrameLowering() 90 CRSaveOffset(computeCRSaveOffset(Subtarget)) {} in PPCFrameLowering() 231 if (Subtarget.is64BitELFABI()) { in getCalleeSavedSpillSlots() 236 if (Subtarget.is32BitELFABI()) { in getCalleeSavedSpillSlots() 241 assert(Subtarget.isAIXABI() && "Unexpected ABI."); in getCalleeSavedSpillSlots() 243 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots() [all …]
H A D	PPCISelLowering.cpp	172 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering() 179 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering() 188 if (!Subtarget.hasEFPU2()) in PPCTargetLowering() 213 if (Subtarget.isISA3_0()) { in PPCTargetLowering() 243 if (!Subtarget.hasSPE()) { in PPCTargetLowering() 259 if (Subtarget.useCRBits()) { in PPCTargetLowering() 262 if (isPPC64 \|\| Subtarget.hasFPCVT()) { in PPCTargetLowering() 336 if (Subtarget.isISA3_0()) { in PPCTargetLowering() 371 if (!Subtarget.hasSPE()) { in PPCTargetLowering() 376 if (Subtarget.hasVSX()) { in PPCTargetLowering() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A D	RISCVFeatures.td	78 def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">, 85 def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">, 93 def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">, 116 def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">, 129 def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">, 136 def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">, 144 def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">, 152 def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">, 163 def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, 171 def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">, [all …]
H A D	RISCVISelLowering.cpp	85 : TargetLowering(TM), Subtarget(STI) { in RISCVTargetLowering() 87 RISCVABI::ABI ABI = Subtarget.getTargetABI(); in RISCVTargetLowering() 91 !Subtarget.hasStdExtF()) { in RISCVTargetLowering() 95 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering() 97 !Subtarget.hasStdExtD()) { in RISCVTargetLowering() 101 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering() 118 MVT XLenVT = Subtarget.getXLenVT(); in RISCVTargetLowering() 122 if (Subtarget.is64Bit() && RV64LegalI32) in RISCVTargetLowering() 125 if (Subtarget.hasStdExtZfhmin()) in RISCVTargetLowering() 127 if (Subtarget in RISCVTargetLowering() 2606 useRVVForFixedLengthVectorVT(MVT VT,const RISCVSubtarget & Subtarget) useRVVForFixedLengthVectorVT() argument 2682 getContainerForFixedLengthVector(const TargetLowering & TLI,MVT VT,const RISCVSubtarget & Subtarget) getContainerForFixedLengthVector() argument 2717 getContainerForFixedLengthVector(SelectionDAG & DAG,MVT VT,const RISCVSubtarget & Subtarget) getContainerForFixedLengthVector() argument 2728 convertToScalableVector(EVT VT,SDValue V,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) convertToScalableVector() argument 2740 convertFromScalableVector(EVT VT,SDValue V,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) convertFromScalableVector() argument 2768 getVLOp(uint64_t NumElts,MVT ContainerVT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getVLOp() argument 2782 getDefaultScalableVLOps(MVT VecVT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getDefaultScalableVLOps() argument 2791 getDefaultVLOps(uint64_t NumElts,MVT ContainerVT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getDefaultVLOps() argument 2804 getDefaultVLOps(MVT VecVT,MVT ContainerVT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getDefaultVLOps() argument 2821 computeVLMAXBounds(MVT VecVT,const RISCVSubtarget & Subtarget) computeVLMAXBounds() argument 2905 lowerFP_TO_INT_SAT(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerFP_TO_INT_SAT() argument 3040 lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() argument 3149 lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() argument 3250 lowerFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerFTRUNC_FCEIL_FFLOOR_FROUND() argument 3278 lowerVectorXRINT(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerVectorXRINT() argument 3302 getVSlidedown(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlidedown() argument 3314 getVSlideup(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlideup() argument 3472 matchSplatAsGather(SDValue SplatVal,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) matchSplatAsGather() argument 3513 lowerBuildVectorViaDominantValues(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerBuildVectorViaDominantValues() argument 3620 lowerBuildVectorOfConstants(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerBuildVectorOfConstants() argument 3921 getPACKOpcode(unsigned DestBW,const RISCVSubtarget & Subtarget) getPACKOpcode() argument 3941 lowerBuildVectorViaPacking(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerBuildVectorViaPacking() argument 4010 lowerBUILD_VECTOR(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerBUILD_VECTOR() argument 4307 lowerScalarSplat(SDValue Passthru,SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarSplat() argument 4345 lowerScalarInsert(SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarInsert() argument 4405 isDeinterleaveShuffle(MVT VT,MVT ContainerVT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget) isDeinterleaveShuffle() argument 4449 isInterleaveShuffle(ArrayRef<int> Mask,MVT VT,int & EvenSrc,int & OddSrc,const RISCVSubtarget & Subtarget) isInterleaveShuffle() argument 4560 getDeinterleaveViaVNSRL(const SDLoc & DL,MVT VT,SDValue Src,bool EvenElts,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) getDeinterleaveViaVNSRL() argument 4620 lowerVECTOR_SHUFFLEAsVSlidedown(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlidedown() argument 4697 lowerVECTOR_SHUFFLEAsVSlideup(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlideup() argument 4741 lowerVECTOR_SHUFFLEAsVSlide1(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlide1() argument 4794 getWideningInterleave(SDValue EvenV,SDValue OddV,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getWideningInterleave() argument 4894 lowerBitreverseShuffle(ShuffleVectorSDNode * SVN,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerBitreverseShuffle() argument 4946 isLegalBitRotate(ShuffleVectorSDNode * SVN,SelectionDAG & DAG,const RISCVSubtarget & Subtarget,MVT & RotateVT,unsigned & RotateAmt) isLegalBitRotate() argument 4969 lowerVECTOR_SHUFFLEAsRotate(ShuffleVectorSDNode * SVN,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerVECTOR_SHUFFLEAsRotate() argument 4997 lowerShuffleViaVRegSplitting(ShuffleVectorSDNode * SVN,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerShuffleViaVRegSplitting() argument 5078 lowerVECTOR_SHUFFLE(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerVECTOR_SHUFFLE() argument 5617 lowerConstant(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerConstant() argument 5657 LowerATOMIC_FENCE(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) LowerATOMIC_FENCE() argument 5860 lowerFMAXIMUM_FMINIMUM(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerFMAXIMUM_FMINIMUM() argument 7558 combineSelectToBinOp(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combineSelectToBinOp() argument 7634 foldBinOpIntoSelectIfProfitable(SDNode * BO,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) foldBinOpIntoSelectIfProfitable() argument 8419 getSmallestVTForIndex(MVT VecVT,unsigned MaxIdx,SDLoc DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getSmallestVTForIndex() argument 8764 lowerVectorIntrinsicScalars(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerVectorIntrinsicScalars() argument 8952 lowerGetVectorLength(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerGetVectorLength() argument 8987 lowerCttzElts(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerCttzElts() argument 9012 const RISCVSubtarget &Subtarget = promoteVCIXScalar() local 9051 const RISCVSubtarget &Subtarget = processVCIXOperands() local 9071 isValidEGW(int EGS,EVT VT,const RISCVSubtarget & Subtarget) isValidEGW() argument 9361 const RISCVSubtarget &Subtarget = getVCIXISDNodeWCHAIN() local 9803 lowerReductionSeq(unsigned RVVOpcode,MVT ResVT,SDValue StartValue,SDValue Vec,SDValue Mask,SDValue VL,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerReductionSeq() argument 9884 getRVVFPReductionOpAndOperands(SDValue Op,SelectionDAG & DAG,EVT EltVT,const RISCVSubtarget & Subtarget) getRVVFPReductionOpAndOperands() argument 12945 combineBinOpOfExtractToReduceTree(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combineBinOpOfExtractToReduceTree() argument 13041 combineBinOpToReduce(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combineBinOpToReduce() argument 13147 transformAddShlImm(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) transformAddShlImm() argument 13203 combineSelectAndUse(SDNode * N,SDValue Slct,SDValue OtherOp,SelectionDAG & DAG,bool AllOnes,const RISCVSubtarget & Subtarget) combineSelectAndUse() argument 13268 combineSelectAndUseCommutative(SDNode * N,SelectionDAG & DAG,bool AllOnes,const RISCVSubtarget & Subtarget) combineSelectAndUseCommutative() argument 13297 transformAddImmMulImm(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) transformAddImmMulImm() argument 13424 performADDCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) performADDCombine() argument 13489 combineSubShiftToOrcB(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combineSubShiftToOrcB() argument 13516 performSUBCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performSUBCombine() argument 13663 performTRUNCATECombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performTRUNCATECombine() argument 13690 performANDCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) performANDCombine() argument 13763 performORCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) performORCombine() argument 13790 performXORCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performXORCombine() argument 13864 expandMul(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) expandMul() argument 14053 performMULCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) performMULCombine() argument 14172 performSETCCCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performSETCCCombine() argument 14219 performSIGN_EXTEND_INREGCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performSIGN_EXTEND_INREGCombine() argument 14803 canFoldToVWWithSameExtensionImpl(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,uint8_t AllowExtMask,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVWWithSameExtensionImpl() argument 14828 canFoldToVWWithSameExtension(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVWWithSameExtension() argument 14841 canFoldToVW_W(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVW_W() argument 14869 canFoldToVWWithSEXT(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVWWithSEXT() argument 14881 canFoldToVWWithZEXT(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVWWithZEXT() argument 14893 canFoldToVWWithFPEXT(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVWWithFPEXT() argument 14905 canFoldToVW_SU(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVW_SU() argument 14982 combineBinOp_VLToVWBinOp_VL(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) combineBinOp_VLToVWBinOp_VL() argument 15122 performVWADDSUBW_VLCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) performVWADDSUBW_VLCombine() argument 15147 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); tryMemPairCombine() local 15198 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); performMemPairCombine() local 15283 performFP_TO_INTCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) performFP_TO_INTCombine() argument 15386 performFP_TO_INT_SATCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) performFP_TO_INT_SATCombine() argument 15448 performBITREVERSECombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performBITREVERSECombine() argument 15543 performVFMADD_VLCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performVFMADD_VLCombine() argument 15602 performSRACombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performSRACombine() argument 15773 combine_CC(SDValue & LHS,SDValue & RHS,SDValue & CC,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combine_CC() argument 15975 useInversedSetcc(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) useInversedSetcc() argument 16006 performSELECTCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performSELECTCombine() argument 16029 performBUILD_VECTORCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const RISCVTargetLowering & TLI) performBUILD_VECTORCombine() argument 16087 performINSERT_VECTOR_ELTCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const RISCVTargetLowering & TLI) performINSERT_VECTOR_ELTCombine() argument 16159 performCONCAT_VECTORSCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const RISCVTargetLowering & TLI) performCONCAT_VECTORSCombine() argument 16284 combineToVWMACC(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combineToVWMACC() argument 16323 __anon765c18b71902(SDNode N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) combineToVWMACC() argument 16525 combineTruncToVnclip(SDNode N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combineTruncToVnclip() argument 18163 emitSplitF64Pseudo(MachineInstr & MI,MachineBasicBlock * BB,const RISCVSubtarget & Subtarget) emitSplitF64Pseudo() argument 18198 emitBuildPairF64Pseudo(MachineInstr & MI,MachineBasicBlock * BB,const RISCVSubtarget & Subtarget) emitBuildPairF64Pseudo() argument 18252 emitQuietFCMP(MachineInstr & MI,MachineBasicBlock * BB,unsigned RelOpcode,unsigned EqOpcode,const RISCVSubtarget & Subtarget) emitQuietFCMP() argument 18289 EmitLoweredCascadedSelect(MachineInstr & First,MachineInstr & Second,MachineBasicBlock * ThisMBB,const RISCVSubtarget & Subtarget) EmitLoweredCascadedSelect() argument 18391 emitSelectPseudo(MachineInstr & MI,MachineBasicBlock * BB,const RISCVSubtarget & Subtarget) emitSelectPseudo() argument 18615 emitFROUND(MachineInstr & MI,MachineBasicBlock * MBB,const RISCVSubtarget & Subtarget) emitFROUND() argument 19315 convertLocVTToValVT(SelectionDAG & DAG,SDValue Val,const CCValAssign & VA,const SDLoc & DL,const RISCVSubtarget & Subtarget) convertLocVTToValVT() argument 19379 convertValVTToLocVT(SelectionDAG & DAG,SDValue Val,const CCValAssign & VA,const SDLoc & DL,const RISCVSubtarget & Subtarget) convertValVTToLocVT() argument 19492 const RISCVSubtarget &Subtarget = TLI.getSubtarget(); CC_RISCV_FastCC() local 19616 const RISCVSubtarget &Subtarget = CC_RISCV_GHC() local [all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A D	RISCVCallLowering.cpp	53 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in assignArg() local 55 if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT, in assignArg() 57 Subtarget.getTargetLowering(), RVVDispatcher)) in assignArg() 69 Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {} in RISCVOutgoingValueHandler() 74 LLT p0 = LLT::pointer(0, Subtarget.getXLen()); in getStackAddress() 75 LLT sXLen = LLT::scalar(Subtarget.getXLen()); in getStackAddress() 170 const RISCVSubtarget &Subtarget; member 199 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in assignArg() local 204 if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT, in assignArg() 206 Subtarget.getTargetLowering(), RVVDispatcher)) in assignArg() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A D	WebAssemblyUtilities.cpp	104 MCContext &Ctx, const WebAssemblySubtarget Subtarget) { in getOrCreateFunctionTableSymbol() argument 111 bool is64 = Subtarget && Subtarget->getTargetTriple().isArch64Bit(); in getOrCreateFunctionTableSymbol() 118 if (!(Subtarget && Subtarget->hasReferenceTypes())) in getOrCreateFunctionTableSymbol() 124 MCContext &Ctx, const WebAssemblySubtarget Subtarget) { in getOrCreateFuncrefCallTableSymbol() argument 143 if (!(Subtarget && Subtarget->hasReferenceTypes())) in getOrCreateFuncrefCallTableSymbol() 187 const WebAssemblySubtarget Subtarget) { in canLowerMultivalueReturn() argument 189 Subtarget->getTargetLowering()->getTargetMachine()); in canLowerMultivalueReturn() 190 return Subtarget->hasMultivalue() && TM.usesMultivalueABI(); in canLowerMultivalueReturn() 194 const WebAssemblySubtarget Subtarget) { in canLowerReturn() argument 195 return ResultSize <= 1 \|\| canLowerMultivalueReturn(Subtarget); in canLowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A D	AVRMCInstLower.cpp	27 const AVRSubtarget &Subtarget) const { in lowerSymbolOperand() 46 AVRMCExpr::create(Subtarget.hasEIJMPCALL() ? AVRMCExpr::VK_AVR_LO8_GS in lowerSymbolOperand() 55 AVRMCExpr::create(Subtarget.hasEIJMPCALL() ? AVRMCExpr::VK_AVR_HI8_GS in lowerSymbolOperand() 70 auto &Subtarget = MI.getParent()->getParent()->getSubtarget<AVRSubtarget>(); in lowerInstruction() local 91 lowerSymbolOperand(MO, Printer.getSymbol(MO.getGlobal()), Subtarget); in lowerInstruction() 95 MO, Printer.GetExternalSymbolSymbol(MO.getSymbolName()), Subtarget); in lowerInstruction() 105 MO, Printer.GetBlockAddressSymbol(MO.getBlockAddress()), Subtarget); in lowerInstruction() 109 Subtarget); in lowerInstruction() 113 Subtarget); in lowerInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A D	AArch64PointerAuth.cpp	44 const AArch64Subtarget Subtarget = nullptr; member in __anonaaaf003a0111::AArch64PointerAuth 78 static void BuildPACM(const AArch64Subtarget &Subtarget, MachineBasicBlock &MBB, in BuildPACM() argument 81 const TargetInstrInfo TII = Subtarget.getInstrInfo(); in BuildPACM() 94 if (MFnI.branchProtectionPAuthLR() && !Subtarget.hasPAuthLR()) in BuildPACM() 125 if (MFnI.branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) { in signLR() 132 BuildPACM(Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup); in signLR() 189 if (Subtarget->hasPAuth() && TerminatorIsCombinable && !NeedsWinCFI && in authenticateLR() 191 if (MFnI->branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) { in authenticateLR() 199 BuildPACM(Subtarget, MBB, TI, DL, MachineInstr::FrameDestroy, PACSym); in authenticateLR() 206 if (MFnI->branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) { in authenticateLR() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A D	CSKYISelDAGToDAG.cpp	28 const CSKYSubtarget Subtarget; member in __anon50a544910111::CSKYDAGToDAGISel 36 Subtarget = &MF.getSubtarget<CSKYSubtarget>(); in runOnMachineFunction() 92 Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(MF); in INITIALIZE_PASS() 102 ReplaceNode(N, CurDAG->getMachineNode(Subtarget->hasE2() ? CSKY::ADDI32 in INITIALIZE_PASS() 290 if (!Subtarget->hasFPUv2DoubleFloat()) in selectBITCAST_TO_LOHI() 315 Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1); in selectAddCarry() 317 Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1}, in selectAddCarry() 321 Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1); in selectAddCarry() 323 Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1}, in selectAddCarry() 326 NewNode = CurDAG->getMachineNode(Subtarget->has2E3() ? CSKY::ADDC32 in selectAddCarry() [all …]
H A D	CSKY.td	24 def HasFPUv2_SF : Predicate<"Subtarget->hasFPUv2SingleFloat()">, 31 def HasFPUv2_DF : Predicate<"Subtarget->hasFPUv2DoubleFloat()">, 37 def HasFdivdu : Predicate<"Subtarget->hasFdivdu()">, 44 def HasFPUv3_HI : Predicate<"Subtarget->hasFPUv3HalfWord()">, 51 def HasFPUv3_HF : Predicate<"Subtarget->hasFPUv3HalfFloat()">, 58 def HasFPUv3_SF : Predicate<"Subtarget->hasFPUv3SingleFloat()">, 65 def HasFPUv3_DF : Predicate<"Subtarget->hasFPUv3DoubleFloat()">, 71 def iHasFLOATE1 : Predicate<"Subtarget->hasFLOATE1()">, 77 def iHasFLOAT1E2 : Predicate<"Subtarget->hasFLOAT1E2()">, 83 def iHasFLOAT1E3 : Predicate<"Subtarget->hasFLOAT1E3()">, [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A D	LoongArch.td	24 : Predicate<"Subtarget->is64Bit()">, 28 : Predicate<"!Subtarget->is64Bit()">, 39 def HasBasicF : Predicate<"Subtarget->hasBasicF()">; 46 def HasBasicD : Predicate<"Subtarget->hasBasicD()">; 52 def HasExtLSX : Predicate<"Subtarget->hasExtLSX()">; 59 def HasExtLASX : Predicate<"Subtarget->hasExtLASX()">; 65 def HasExtLVZ : Predicate<"Subtarget->hasExtLVZ()">; 71 def HasExtLBT : Predicate<"Subtarget->hasExtLBT()">; 78 : Predicate<"Subtarget->hasLaGlobalWithPcrel()">, 87 : Predicate<"Subtarget->hasLaGlobalWithAbs()">, [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A D	SparcRegisterInfo.cpp	54 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() 65 if (!Subtarget.is64Bit()) in getReservedRegs() 80 if (ReserveAppRegisters \|\| !Subtarget.is64Bit()) in getReservedRegs() 88 if (!Subtarget.isV9()) { in getReservedRegs() 117 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in replaceFI() 118 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in replaceFI() 183 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() 192 if (!Subtarget.isV9() \|\| !Subtarget.hasHardQuad()) { in eliminateFrameIndex() 194 const TargetInstrInfo &TII = *Subtarget in eliminateFrameIndex() 56 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); getReservedRegs() local 107 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); getPointerRegClass() local 173 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); eliminateFrameIndex() local [all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A D	SystemZRegisterInfo.cpp	79 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getRegAllocationHints() local 80 const TargetRegisterInfo TRI = Subtarget.getRegisterInfo(); in getRegAllocationHints() 192 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local 193 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_SaveList in getCalleeSavedRegs() 199 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local 203 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList in getCalleeSavedRegs() 215 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local 216 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_RegMask in getCallPreservedMask() 223 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local 227 return Subtarget in getCallPreservedMask() 242 const SystemZSubtarget Subtarget = &MF->getSubtarget<SystemZSubtarget>(); getCalleeSavedRegs() local 252 const SystemZSubtarget Subtarget = &MF.getSubtarget<SystemZSubtarget>(); getCallPreservedMask() local 261 const SystemZSubtarget Subtarget = &MF.getSubtarget<SystemZSubtarget>(); getReservedRegs() local 452 const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>(); getFrameRegister() local [all...]

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