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Searched refs:Subtarget (Results 1 – 25 of 326) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrPredicates.td35 def HasEGPR : Predicate<"Subtarget->hasEGPR()">;
36 def NoEGPR : Predicate<"!Subtarget->hasEGPR()">;
46 def HasNDD : Predicate<"Subtarget->hasNDD()">;
47 def NoNDD : Predicate<"!Subtarget->hasNDD()">;
48 def HasZU : Predicate<"Subtarget->hasZU()">;
49 def HasCF : Predicate<"Subtarget->hasCF()">;
50 def HasCMOV : Predicate<"Subtarget->canUseCMOV()">;
51 def NoCMOV : Predicate<"!Subtarget->canUseCMOV()">;
52 def HasNOPL : Predicate<"Subtarget->hasNOPL()">;
53 def HasMMX : Predicate<"Subtarget->hasMMX()">;
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H A DX86SelectionDAGInfo.cpp41 static MVT getOptimalRepType(const X86Subtarget &Subtarget, Align Alignment) { in getOptimalRepType() argument
53 return Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in getOptimalRepType()
74 static SDValue emitRepstos(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepstos() argument
77 const bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in emitRepstos()
111 static SDValue emitRepstosB(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepstosB() argument
114 return emitRepstos(Subtarget, DAG, dl, Chain, Dst, Val, in emitRepstosB()
123 const X86Subtarget &Subtarget, in emitConstantSizeRepstos() argument
143 return emitRepstos(Subtarget, DAG, dl, Chain, Dst, Val, in emitConstantSizeRepstos()
147 return emitRepstosB(Subtarget, DAG, dl, Chain, Dst, Val, Size); in emitConstantSizeRepstos()
150 if (Size > Subtarget.getMaxInlineSizeThreshold()) in emitConstantSizeRepstos()
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H A DX86ISelLoweringCall.cpp71 const X86Subtarget &Subtarget) { in handleMaskRegisterForCallingConv() argument
86 if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall)) in handleMaskRegisterForCallingConv()
89 if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) { in handleMaskRegisterForCallingConv()
90 if (Subtarget.useAVX512Regs()) in handleMaskRegisterForCallingConv()
96 if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) || in handleMaskRegisterForCallingConv()
107 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) { in getRegisterTypeForCallingConv()
113 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget); in getRegisterTypeForCallingConv()
123 if ((VT == MVT::f64 || VT == MVT::f80) && !Subtarget.is64Bit() && in getRegisterTypeForCallingConv()
124 !Subtarget.hasX87()) in getRegisterTypeForCallingConv()
143 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) { in getNumRegistersForCallingConv()
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H A DX86ISelLowering.cpp134 : TargetLowering(TM), Subtarget(STI) { in X86TargetLowering()
135 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87(); in X86TargetLowering()
152 if (Subtarget.isAtom()) in X86TargetLowering()
154 else if (Subtarget.is64Bit()) in X86TargetLowering()
158 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in X86TargetLowering()
163 if (Subtarget.hasSlowDivide32()) in X86TargetLowering()
165 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit()) in X86TargetLowering()
169 if (Subtarget.canUseCMPXCHG16B()) in X86TargetLowering()
171 else if (Subtarget.canUseCMPXCHG8B()) in X86TargetLowering()
176 setMaxDivRemBitWidthSupported(Subtarget.is64Bit() ? 128 : 64); in X86TargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMPredicates.td9 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
11 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
12 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
14 def NoV5T : Predicate<"!Subtarget->hasV5TOps()">;
15 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
17 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
19 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
20 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
23 def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">,
26 def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">,
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H A DARMMachineFunctionInfo.cpp29 const ARMSubtarget *Subtarget) { in GetBranchTargetEnforcement() argument
30 if (!Subtarget->isMClass() || !Subtarget->hasV7Ops()) in GetBranchTargetEnforcement()
55 const ARMSubtarget *Subtarget) in ARMFunctionInfo() argument
56 : isThumb(Subtarget->isThumb()), hasThumb2(Subtarget->hasThumb2()), in ARMFunctionInfo()
59 BranchTargetEnforcement(GetBranchTargetEnforcement(F, Subtarget)) { in ARMFunctionInfo()
60 if (Subtarget->isMClass() && Subtarget->hasV7Ops()) in ARMFunctionInfo()
H A DARMSelectionDAGInfo.cpp44 const ARMSubtarget &Subtarget = in EmitSpecializedLibcall() local
46 const ARMTargetLowering *TLI = Subtarget.getTargetLowering(); in EmitSpecializedLibcall()
146 static bool shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget, in shouldGenerateInlineTPLoop() argument
166 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold() && in shouldGenerateInlineTPLoop()
168 Subtarget.getMaxMemcpyTPInlineSizeThreshold()) in shouldGenerateInlineTPLoop()
177 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemcpy() local
181 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemcpy()
182 shouldGenerateInlineTPLoop(Subtarget, DAG, ConstantSize, Alignment, true)) in EmitTargetCodeForMemcpy()
196 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy()
207 const unsigned MaxLoadsInLDM = Subtarget.isThumb1Only() ? 4 : 6; in EmitTargetCodeForMemcpy()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp94 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>(); in getCalleeSavedRegs() local
97 if (Subtarget.hasMips64()) in getCalleeSavedRegs()
98 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList in getCalleeSavedRegs()
101 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList in getCalleeSavedRegs()
105 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs()
108 if (Subtarget.isABI_N64()) in getCalleeSavedRegs()
111 if (Subtarget.isABI_N32()) in getCalleeSavedRegs()
114 if (Subtarget.isFP64bit()) in getCalleeSavedRegs()
117 if (Subtarget.isFPXX()) in getCalleeSavedRegs()
126 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); in getCallPreservedMask() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td23 // Subtarget Features (device properties)
1158 // Subtarget Features (options and debugging)
2090 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
2094 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
2095 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
2099 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
2100 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
2101 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
2105 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
2106 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td86 def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
92 def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
99 def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
122 def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
133 def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
139 def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
146 def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
153 def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
163 def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
170 def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
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H A DRISCVISelLowering.cpp91 : TargetLowering(TM), Subtarget(STI) { in RISCVTargetLowering()
93 RISCVABI::ABI ABI = Subtarget.getTargetABI(); in RISCVTargetLowering()
97 !Subtarget.hasStdExtF()) { in RISCVTargetLowering()
101 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
103 !Subtarget.hasStdExtD()) { in RISCVTargetLowering()
107 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
124 MVT XLenVT = Subtarget.getXLenVT(); in RISCVTargetLowering()
129 if (Subtarget.hasStdExtZfhmin()) in RISCVTargetLowering()
131 if (Subtarget.hasStdExtZfbfmin()) in RISCVTargetLowering()
133 if (Subtarget.hasStdExtF()) in RISCVTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaFeatures.td8 def HasDensity : Predicate<"Subtarget->hasDensity()">,
13 def HasSingleFloat : Predicate<"Subtarget->hasSingleFloat()">,
18 def HasWindowed : Predicate<"Subtarget->hasWindowed()">,
23 def HasMAC16 : Predicate<"Subtarget->hasMAC16()">,
28 def HasBoolean : Predicate<"Subtarget->hasBoolean()">,
33 def HasLoop : Predicate<"Subtarget->hasLoop()">,
38 def HasSEXT : Predicate<"Subtarget->hasSEXT()">,
43 def HasCLAMPS : Predicate<"Subtarget->hasCLAMPS()">,
48 def HasNSA : Predicate<"Subtarget->hasNSA()">,
53 def HasMINMAX : Predicate<"Subtarget->hasMINMAX()">,
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCLowerMASSVEntries.cpp54 static StringRef getCPUSuffix(const PPCSubtarget *Subtarget);
56 const PPCSubtarget *Subtarget);
59 const PPCSubtarget *Subtarget);
75 StringRef PPCLowerMASSVEntries::getCPUSuffix(const PPCSubtarget *Subtarget) { in getCPUSuffix() argument
77 if (!Subtarget) in getCPUSuffix()
80 if (Subtarget->isAIXABI() && Subtarget->hasP10Vector()) in getCPUSuffix()
82 if (Subtarget->hasP9Vector()) in getCPUSuffix()
84 if (Subtarget->hasP8Vector()) in getCPUSuffix()
86 if (Subtarget->isAIXABI()) in getCPUSuffix()
98 const PPCSubtarget *Subtarget) { in createMASSVFuncName() argument
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H A DPPCRegisterInfo.cpp184 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); in getCalleeSavedRegs() local
186 if (!TM.isPPC64() && Subtarget.isAIXABI()) in getCalleeSavedRegs()
188 if (Subtarget.hasVSX()) { in getCalleeSavedRegs()
189 if (Subtarget.pairedVectorMemops()) in getCalleeSavedRegs()
191 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) in getCalleeSavedRegs()
195 if (Subtarget.hasAltivec()) { in getCalleeSavedRegs()
196 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) in getCalleeSavedRegs()
211 !Subtarget.isUsingPCRelativeCalls(); in getCalleeSavedRegs()
215 if (Subtarget.isAIXABI()) in getCalleeSavedRegs()
218 if (Subtarget.pairedVectorMemops()) in getCalleeSavedRegs()
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H A DPPCFrameLowering.cpp85 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering()
86 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), in PPCFrameLowering()
87 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), in PPCFrameLowering()
88 LinkageSize(computeLinkageSize(Subtarget)), in PPCFrameLowering()
89 BasePointerSaveOffset(computeBasePointerSaveOffset(Subtarget)), in PPCFrameLowering()
90 CRSaveOffset(computeCRSaveOffset(Subtarget)) {} in PPCFrameLowering()
231 if (Subtarget.is64BitELFABI()) { in getCalleeSavedSpillSlots()
236 if (Subtarget.is32BitELFABI()) { in getCalleeSavedSpillSlots()
241 assert(Subtarget.isAIXABI() && "Unexpected ABI."); in getCalleeSavedSpillSlots()
243 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
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H A DPPCISelLowering.cpp175 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering()
182 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering()
184 const MVT RegVT = Subtarget.getScalarIntVT(); in PPCTargetLowering()
192 if (!Subtarget.hasEFPU2()) in PPCTargetLowering()
209 if (!Subtarget.hasP10Vector()) { in PPCTargetLowering()
235 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
268 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
275 if (Subtarget.useCRBits()) { in PPCTargetLowering()
278 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
344 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp61 Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {} in RISCVOutgoingValueHandler()
66 LLT p0 = LLT::pointer(0, Subtarget.getXLen()); in getStackAddress()
67 LLT sXLen = LLT::scalar(Subtarget.getXLen()); in getStackAddress()
172 const RISCVSubtarget &Subtarget; member
211 Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {} in RISCVIncomingValueHandler()
220 return MIRBuilder.buildFrameIndex(LLT::pointer(0, Subtarget.getXLen()), FI) in getStackAddress()
296 const RISCVSubtarget &Subtarget; member
328 const RISCVSubtarget &Subtarget) { in isLegalElementTypeForRVV() argument
330 return Subtarget.is64Bit() ? Subtarget.hasVInstructionsI64() : true; in isLegalElementTypeForRVV()
335 return Subtarget.hasVInstructionsI64(); in isLegalElementTypeForRVV()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyUtilities.cpp105 MCContext &Ctx, const WebAssemblySubtarget *Subtarget) { in getOrCreateFunctionTableSymbol() argument
112 bool is64 = Subtarget && Subtarget->getTargetTriple().isArch64Bit(); in getOrCreateFunctionTableSymbol()
119 if (!(Subtarget && Subtarget->hasCallIndirectOverlong())) in getOrCreateFunctionTableSymbol()
125 MCContext &Ctx, const WebAssemblySubtarget *Subtarget) { in getOrCreateFuncrefCallTableSymbol() argument
144 if (!(Subtarget && Subtarget->hasCallIndirectOverlong())) in getOrCreateFuncrefCallTableSymbol()
188 const WebAssemblySubtarget *Subtarget) { in canLowerMultivalueReturn() argument
190 Subtarget->getTargetLowering()->getTargetMachine()); in canLowerMultivalueReturn()
191 return Subtarget->hasMultivalue() && TM.usesMultivalueABI(); in canLowerMultivalueReturn()
195 const WebAssemblySubtarget *Subtarget) { in canLowerReturn() argument
196 return ResultSize <= 1 || canLowerMultivalueReturn(Subtarget); in canLowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRMCInstLower.cpp27 const AVRSubtarget &Subtarget) const { in lowerSymbolOperand()
45 Expr = AVRMCExpr::create(Subtarget.hasEIJMPCALL() ? AVR::S_LO8_GS in lowerSymbolOperand()
53 Expr = AVRMCExpr::create(Subtarget.hasEIJMPCALL() ? AVR::S_HI8_GS in lowerSymbolOperand()
68 auto &Subtarget = MI.getParent()->getParent()->getSubtarget<AVRSubtarget>(); in lowerInstruction() local
89 lowerSymbolOperand(MO, Printer.getSymbol(MO.getGlobal()), Subtarget); in lowerInstruction()
93 MO, Printer.GetExternalSymbolSymbol(MO.getSymbolName()), Subtarget); in lowerInstruction()
103 MO, Printer.GetBlockAddressSymbol(MO.getBlockAddress()), Subtarget); in lowerInstruction()
107 Subtarget); in lowerInstruction()
111 Subtarget); in lowerInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArch.td23 def Has32S : Predicate<"Subtarget->has32S()">;
33 : Predicate<"Subtarget->is64Bit()">,
37 : Predicate<"!Subtarget->is64Bit()">,
48 def HasBasicF : Predicate<"Subtarget->hasBasicF()">;
55 def HasBasicD : Predicate<"Subtarget->hasBasicD()">;
61 def HasExtLSX : Predicate<"Subtarget->hasExtLSX()">;
68 def HasExtLASX : Predicate<"Subtarget->hasExtLASX()">;
74 def HasExtLVZ : Predicate<"Subtarget->hasExtLVZ()">;
80 def HasExtLBT : Predicate<"Subtarget->hasExtLBT()">;
87 : Predicate<"Subtarget->hasLaGlobalWithPcrel()">,
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp28 const CSKYSubtarget *Subtarget; member in __anon50a544910111::CSKYDAGToDAGISel
36 Subtarget = &MF.getSubtarget<CSKYSubtarget>(); in runOnMachineFunction()
92 Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF); in INITIALIZE_PASS()
102 ReplaceNode(N, CurDAG->getMachineNode(Subtarget->hasE2() ? CSKY::ADDI32 in INITIALIZE_PASS()
290 if (!Subtarget->hasFPUv2DoubleFloat()) in selectBITCAST_TO_LOHI()
315 Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1); in selectAddCarry()
317 Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1}, in selectAddCarry()
321 Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1); in selectAddCarry()
323 Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1}, in selectAddCarry()
326 NewNode = CurDAG->getMachineNode(Subtarget->has2E3() ? CSKY::ADDC32 in selectAddCarry()
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H A DCSKY.td24 def HasFPUv2_SF : Predicate<"Subtarget->hasFPUv2SingleFloat()">,
31 def HasFPUv2_DF : Predicate<"Subtarget->hasFPUv2DoubleFloat()">,
37 def HasFdivdu : Predicate<"Subtarget->hasFdivdu()">,
44 def HasFPUv3_HI : Predicate<"Subtarget->hasFPUv3HalfWord()">,
51 def HasFPUv3_HF : Predicate<"Subtarget->hasFPUv3HalfFloat()">,
58 def HasFPUv3_SF : Predicate<"Subtarget->hasFPUv3SingleFloat()">,
65 def HasFPUv3_DF : Predicate<"Subtarget->hasFPUv3DoubleFloat()">,
71 def iHasFLOATE1 : Predicate<"Subtarget->hasFLOATE1()">,
77 def iHasFLOAT1E2 : Predicate<"Subtarget->hasFLOAT1E2()">,
83 def iHasFLOAT1E3 : Predicate<"Subtarget->hasFLOAT1E3()">,
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PointerAuth.cpp38 const AArch64Subtarget *Subtarget = nullptr; member in __anonaaaf003a0111::AArch64PointerAuth
76 static void BuildPACM(const AArch64Subtarget &Subtarget, MachineBasicBlock &MBB, in BuildPACM() argument
79 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in BuildPACM()
90 if (MFnI.branchProtectionPAuthLR() && !Subtarget.hasPAuthLR()) in BuildPACM()
133 if (MFnI.branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) { in signLR()
141 BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup); in signLR()
184 if (Subtarget->hasPAuth() && TerminatorIsCombinable && !NeedsWinCFI && in authenticateLR()
186 if (MFnI->branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) { in authenticateLR()
195 BuildPACM(*Subtarget, MBB, TI, DL, MachineInstr::FrameDestroy, PACSym); in authenticateLR()
202 if (MFnI->branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) { in authenticateLR()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp78 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getRegAllocationHints() local
79 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in getRegAllocationHints()
191 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
192 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_SaveList in getCalleeSavedRegs()
198 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
202 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList in getCalleeSavedRegs()
214 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
215 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_RegMask in getCallPreservedMask()
222 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
226 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask in getCallPreservedMask()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp54 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() local
65 if (!Subtarget.is64Bit()) in getReservedRegs()
80 if (ReserveAppRegisters || !Subtarget.is64Bit()) in getReservedRegs()
88 if (!Subtarget.isV9()) { in getReservedRegs()
117 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getPointerRegClass() local
118 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
183 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() local
192 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
194 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
206 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()

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