Lines Matching refs:Subtarget
172 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering()
179 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering()
188 if (!Subtarget.hasEFPU2()) in PPCTargetLowering()
213 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
243 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
259 if (Subtarget.useCRBits()) { in PPCTargetLowering()
262 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
336 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
371 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
376 if (Subtarget.hasVSX()) { in PPCTargetLowering()
381 if (Subtarget.hasFSQRT()) { in PPCTargetLowering()
386 if (Subtarget.hasFPRND()) { in PPCTargetLowering()
427 if (Subtarget.hasSPE()) { in PPCTargetLowering()
435 if (Subtarget.hasSPE()) in PPCTargetLowering()
441 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
442 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() && in PPCTargetLowering()
443 Subtarget.hasFRE())) in PPCTargetLowering()
446 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
447 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() && in PPCTargetLowering()
448 Subtarget.hasFRES())) in PPCTargetLowering()
451 if (Subtarget.hasFCPSGN()) { in PPCTargetLowering()
459 if (Subtarget.hasFPRND()) { in PPCTargetLowering()
473 if (Subtarget.isISA3_1()) { in PPCTargetLowering()
480 (Subtarget.hasP9Vector() && Subtarget.isPPC64()) ? Custom : Expand); in PPCTargetLowering()
484 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
492 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) { in PPCTargetLowering()
504 if (!Subtarget.useCRBits()) { in PPCTargetLowering()
517 if (!Subtarget.useCRBits()) in PPCTargetLowering()
520 if (Subtarget.hasFPU()) { in PPCTargetLowering()
531 if (!Subtarget.useCRBits()) in PPCTargetLowering()
536 if (Subtarget.hasSPE()) { in PPCTargetLowering()
560 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
617 if (Subtarget.is64BitELFABI()) { in PPCTargetLowering()
628 } else if (Subtarget.is32BitELFABI()) { in PPCTargetLowering()
636 if (Subtarget.is32BitELFABI()) in PPCTargetLowering()
668 if (Subtarget.hasSPE()) { in PPCTargetLowering()
690 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
705 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) { in PPCTargetLowering()
711 if (Subtarget.hasSPE()) { in PPCTargetLowering()
721 if (Subtarget.hasFPCVT()) { in PPCTargetLowering()
722 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
743 if (Subtarget.use64BitRegs()) { in PPCTargetLowering()
761 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
768 if (Subtarget.hasVSX()) { in PPCTargetLowering()
775 if (Subtarget.hasAltivec()) { in PPCTargetLowering()
804 if (Subtarget.hasVSX()) { in PPCTargetLowering()
810 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) { in PPCTargetLowering()
820 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128)) in PPCTargetLowering()
894 if (!Subtarget.hasP8Vector()) { in PPCTargetLowering()
918 Subtarget.useCRBits() ? Legal : Expand); in PPCTargetLowering()
936 if (Subtarget.hasAltivec()) in PPCTargetLowering()
940 if (Subtarget.hasP8Altivec()) in PPCTargetLowering()
951 if (Subtarget.hasVSX()) { in PPCTargetLowering()
957 if (Subtarget.hasP8Altivec()) in PPCTargetLowering()
962 if (Subtarget.isISA3_1()) { in PPCTargetLowering()
1000 if (Subtarget.hasVSX()) { in PPCTargetLowering()
1003 if (Subtarget.hasP8Vector()) { in PPCTargetLowering()
1007 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
1058 if (Subtarget.hasP8Vector()) in PPCTargetLowering()
1067 if (Subtarget.hasP8Altivec()) { in PPCTargetLowering()
1094 if (Subtarget.isISA3_1()) in PPCTargetLowering()
1197 if (Subtarget.hasP8Altivec()) { in PPCTargetLowering()
1202 if (Subtarget.hasP9Vector()) { in PPCTargetLowering()
1207 if (Subtarget.useCRBits()) { in PPCTargetLowering()
1266 } else if (Subtarget.hasVSX()) { in PPCTargetLowering()
1310 if (Subtarget.hasP9Altivec()) { in PPCTargetLowering()
1311 if (Subtarget.isISA3_1()) { in PPCTargetLowering()
1334 if (Subtarget.hasP10Vector()) { in PPCTargetLowering()
1339 if (Subtarget.pairedVectorMemops()) { in PPCTargetLowering()
1344 if (Subtarget.hasMMA()) { in PPCTargetLowering()
1345 if (Subtarget.isISAFuture()) in PPCTargetLowering()
1354 if (Subtarget.has64BitSupport()) in PPCTargetLowering()
1357 if (Subtarget.isISA3_1()) in PPCTargetLowering()
1375 if (Subtarget.hasAltivec()) { in PPCTargetLowering()
1392 if (Subtarget.hasFPCVT()) in PPCTargetLowering()
1395 if (Subtarget.useCRBits()) in PPCTargetLowering()
1404 if (Subtarget.useCRBits()) { in PPCTargetLowering()
1434 if (Subtarget.isAIXABI()) { in PPCTargetLowering()
1443 if (Subtarget.useCRBits()) { in PPCTargetLowering()
1456 switch (Subtarget.getCPUDirective()) { in PPCTargetLowering()
1479 if (Subtarget.enableMachineScheduler()) in PPCTargetLowering()
1488 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc || in PPCTargetLowering()
1489 Subtarget.getCPUDirective() == PPC::DIR_E5500) { in PPCTargetLowering()
1496 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) { in PPCTargetLowering()
1514 PredictableSelectIsExpensive = Subtarget.isPredictableSelectIsExpensive(); in PPCTargetLowering()
1632 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4); in getByValTypeAlignment()
1633 if (Subtarget.hasAltivec()) in getByValTypeAlignment()
1639 return Subtarget.useSoftFloat(); in useSoftFloat()
1643 return Subtarget.hasSPE(); in hasSPE()
1652 if (!Subtarget.isPPC64() || !Subtarget.hasVSX()) in shallExtractConstSplatVectorElementToStore()
1659 Index = Subtarget.isLittleEndian() ? 2 : 1; in shallExtractConstSplatVectorElementToStore()
1663 Index = Subtarget.isLittleEndian() ? 1 : 0; in shallExtractConstSplatVectorElementToStore()
1847 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32; in getSetCCResultType()
1956 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>(); in isVPKUDUMShuffleMask() local
1957 if (!Subtarget.hasP8Vector()) in isVPKUDUMShuffleMask()
2867 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegImm()
2974 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegRegOnly()
3073 if (isLoad && usePartialVectorLoads(N, Subtarget)) { in getPreIndexedAddressParts()
3135 static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget, in getLabelAccessInfo() argument
3178 const bool Is64Bit = Subtarget.isPPC64(); in getTOCEntry()
3181 : Subtarget.isAIXABI() in getTOCEntry()
3199 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerConstantPool()
3200 if (Subtarget.isUsingPCRelativeCalls()) { in LowerConstantPool()
3214 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); in LowerConstantPool()
3216 if (IsPIC && Subtarget.isSVR4ABI()) { in LowerConstantPool()
3242 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) in isJumpTableRelative()
3249 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBase()
3266 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBaseExpr()
3283 if (Subtarget.isUsingPCRelativeCalls()) { in LowerJumpTable()
3294 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerJumpTable()
3302 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); in LowerJumpTable()
3304 if (IsPIC && Subtarget.isSVR4ABI()) { in LowerJumpTable()
3322 if (Subtarget.isUsingPCRelativeCalls()) { in LowerBlockAddress()
3333 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerBlockAddress()
3340 if (Subtarget.is32BitELFABI() && isPositionIndependent()) in LowerBlockAddress()
3347 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); in LowerBlockAddress()
3355 if (Subtarget.isAIXABI()) in LowerGlobalTLSAddress()
3419 bool Is64Bit = Subtarget.isPPC64(); in LowerGlobalTLSAddressAIX()
3423 if (Subtarget.hasAIXShLibTLSModelOpt()) in LowerGlobalTLSAddressAIX()
3429 bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS(); in LowerGlobalTLSAddressAIX()
3486 bool HasAIXSmallLocalDynamicTLS = Subtarget.hasAIXSmallLocalDynamicTLS(); in LowerGlobalTLSAddressAIX()
3562 bool is64bit = Subtarget.isPPC64(); in LowerGlobalTLSAddressLinux()
3570 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalTLSAddressLinux()
3591 bool IsPCRel = Subtarget.isUsingPCRelativeCalls(); in LowerGlobalTLSAddressLinux()
3622 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalTLSAddressLinux()
3646 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalTLSAddressLinux()
3686 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerGlobalAddress()
3687 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalAddress()
3709 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV); in LowerGlobalAddress()
3711 if (IsPIC && Subtarget.isSVR4ABI()) { in LowerGlobalAddress()
3738 assert(!Subtarget.hasP9Vector() && in LowerSETCC()
3811 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); in LowerVAARG()
3902 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"); in LowerVACOPY()
3914 if (Subtarget.isAIXABI()) in LowerADJUST_TRAMPOLINE()
3973 if (Subtarget.isAIXABI()) in LowerINIT_TRAMPOLINE()
4017 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) { in LowerVASTART()
4217 if (Subtarget.isAIXABI()) in LowerFormalArguments()
4220 if (Subtarget.is64BitELFABI()) in LowerFormalArguments()
4223 assert(Subtarget.is32BitELFABI()); in LowerFormalArguments()
4278 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_32SVR4()
4302 if (Subtarget.hasP8Vector()) in LowerFormalArguments_32SVR4()
4304 else if (Subtarget.hasSPE()) in LowerFormalArguments_32SVR4()
4310 if (Subtarget.hasVSX()) in LowerFormalArguments_32SVR4()
4312 else if (Subtarget.hasSPE()) in LowerFormalArguments_32SVR4()
4335 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) { in LowerFormalArguments_32SVR4()
4341 if (!Subtarget.isLittleEndian()) in LowerFormalArguments_32SVR4()
4395 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea); in LowerFormalArguments_32SVR4()
4499 bool isELFv2ABI = Subtarget.isELFv2ABI(); in LowerFormalArguments_64SVR4()
4500 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerFormalArguments_64SVR4()
4513 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_64SVR4()
4735 Subtarget.hasP8Vector() in LowerFormalArguments_64SVR4()
4739 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() in LowerFormalArguments_64SVR4()
4831 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea); in LowerFormalArguments_64SVR4()
4966 needStackSlotPassParameters(const PPCSubtarget &Subtarget, in needStackSlotPassParameters() argument
4968 assert(Subtarget.is64BitELFABI()); in needStackSlotPassParameters()
4971 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in needStackSlotPassParameters()
5091 if (CallerCC != CalleeCC && needStackSlotPassParameters(Subtarget, Outs)) in IsEligibleForTailCallOptimization_64SVR4()
5103 if (!Subtarget.isUsingPCRelativeCalls() && in IsEligibleForTailCallOptimization_64SVR4()
5108 if (!Subtarget.isUsingPCRelativeCalls() && in IsEligibleForTailCallOptimization_64SVR4()
5125 needStackSlotPassParameters(Subtarget, Outs)) in IsEligibleForTailCallOptimization_64SVR4()
5127 else if (!CB && needStackSlotPassParameters(Subtarget, Outs)) in IsEligibleForTailCallOptimization_64SVR4()
5220 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); in EmitTailCallStoreFPAndRetAddr() local
5221 const PPCFrameLowering *FL = Subtarget.getFrameLowering(); in EmitTailCallStoreFPAndRetAddr()
5222 bool isPPC64 = Subtarget.isPPC64(); in EmitTailCallStoreFPAndRetAddr()
5261 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
5354 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold) in LowerCallResult()
5365 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { in LowerCallResult()
5375 if (!Subtarget.isLittleEndian()) in LowerCallResult()
5410 const PPCSubtarget &Subtarget, bool isPatchPoint) { in isIndirectCall() argument
5426 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI() && in isIndirectCall()
5434 static inline bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget) { in isTOCSaveRestoreRequired() argument
5435 return Subtarget.isAIXABI() || in isTOCSaveRestoreRequired()
5436 (Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()); in isTOCSaveRestoreRequired()
5441 const PPCSubtarget &Subtarget, in getCallOpcode() argument
5458 RetOpc = isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC in getCallOpcode()
5460 } else if (Subtarget.isUsingPCRelativeCalls()) { in getCallOpcode()
5461 assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI."); in getCallOpcode()
5463 } else if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI()) { in getCallOpcode()
5503 const SDLoc &dl, const PPCSubtarget &Subtarget) { in transformCallee() argument
5504 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI()) in transformCallee()
5522 Subtarget.is32BitELFABI() && !isLocalCallee() && in transformCallee()
5523 Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_; in transformCallee()
5526 const TargetMachine &TM = Subtarget.getTargetMachine(); in transformCallee()
5540 if (Subtarget.isAIXABI()) { in transformCallee()
5550 if (Subtarget.isAIXABI()) { in transformCallee()
5613 const PPCSubtarget &Subtarget) { in prepareDescriptorIndirectCall() argument
5642 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors() in prepareDescriptorIndirectCall()
5650 const MCRegister EnvPtrReg = Subtarget.getEnvironmentPointerRegister(); in prepareDescriptorIndirectCall()
5651 const MCRegister TOCReg = Subtarget.getTOCPointerRegister(); in prepareDescriptorIndirectCall()
5654 const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset(); in prepareDescriptorIndirectCall()
5655 const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset(); in prepareDescriptorIndirectCall()
5657 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall()
5658 const Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4); in prepareDescriptorIndirectCall()
5687 assert((!hasNest || !Subtarget.isAIXABI()) && in prepareDescriptorIndirectCall()
5706 const PPCSubtarget &Subtarget) { in buildCallOperands() argument
5707 const bool IsPPC64 = Subtarget.isPPC64(); in buildCallOperands()
5729 if (isTOCSaveRestoreRequired(Subtarget)) { in buildCallOperands()
5730 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister(); in buildCallOperands()
5733 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset(); in buildCallOperands()
5740 if (Subtarget.usesFunctionDescriptors() && !CFlags.HasNest) in buildCallOperands()
5741 Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(), in buildCallOperands()
5763 if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) && in buildCallOperands()
5764 !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls()) in buildCallOperands()
5765 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT)); in buildCallOperands()
5768 if (CFlags.IsVarArg && Subtarget.is32BitELFABI()) in buildCallOperands()
5772 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in buildCallOperands()
5790 if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) || in FinishCall()
5791 Subtarget.isAIXABI()) in FinishCall()
5796 Subtarget, DAG.getTarget(), CB ? CB->isStrictFP() : false); in FinishCall()
5799 Callee = transformCallee(Callee, DAG, dl, Subtarget); in FinishCall()
5800 else if (Subtarget.usesFunctionDescriptors()) in FinishCall()
5802 dl, CFlags.HasNest, Subtarget); in FinishCall()
5809 SPDiff, Subtarget); in FinishCall()
5820 (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && in FinishCall()
5880 if (Subtarget.useLongCalls() && !(CB && CB->isMustTailCall())) in isEligibleForTCO()
5883 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) in isEligibleForTCO()
5929 assert((Subtarget.isUsingPCRelativeCalls() || in LowerCall()
5946 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) && in LowerCall()
5952 isIndirectCall(Callee, DAG, Subtarget, isPatchPoint), in LowerCall()
5954 Subtarget.is64BitELFABI() && in LowerCall()
5958 if (Subtarget.isAIXABI()) in LowerCall()
5962 assert(Subtarget.isSVR4ABI()); in LowerCall()
5963 if (Subtarget.isPPC64()) in LowerCall()
6010 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(), in LowerCall_32SVR4()
6144 if (Subtarget.hasSPE() && Arg.getValueType() == MVT::f64) { in LowerCall_32SVR4()
6145 bool IsLE = Subtarget.isLittleEndian(); in LowerCall_32SVR4()
6231 bool isELFv2ABI = Subtarget.isELFv2ABI(); in LowerCall_64SVR4()
6232 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerCall_64SVR4()
6260 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerCall_64SVR4()
6379 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes); in LowerCall_64SVR4()
6772 if (isTOCSaveRestoreRequired(Subtarget)) { in LowerCall_64SVR4()
6778 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset(); in LowerCall_64SVR4()
6846 const PPCSubtarget &Subtarget = static_cast<const PPCSubtarget &>( in CC_AIX() local
6848 const bool IsPPC64 = Subtarget.isPPC64(); in CC_AIX()
7202 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>(); in LowerFormalArguments_AIX() local
7204 const bool IsPPC64 = Subtarget.isPPC64(); in LowerFormalArguments_AIX()
7216 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_AIX()
7277 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
7278 Subtarget.hasVSX())); in LowerFormalArguments_AIX()
7354 const PPCFrameLowering *FL = Subtarget.getFrameLowering(); in LowerFormalArguments_AIX()
7416 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
7417 Subtarget.hasVSX())); in LowerFormalArguments_AIX()
7444 EnsureStackAlignment(Subtarget.getFrameLowering(), CallerReservedArea); in LowerFormalArguments_AIX()
7504 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>(); in LowerCall_AIX() local
7515 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerCall_AIX()
7516 const bool IsPPC64 = Subtarget.isPPC64(); in LowerCall_AIX()
7778 const MCRegister TOCBaseReg = Subtarget.getTOCPointerRegister(); in LowerCall_AIX()
7779 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister(); in LowerCall_AIX()
7780 const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerCall_AIX()
7782 Subtarget.getFrameLowering()->getTOCSaveOffset(); in LowerCall_AIX()
7815 Outs, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold) in CanLowerReturn()
7830 (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold) in LowerReturn()
7857 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { in LowerReturn()
7858 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerReturn()
7911 bool isPPC64 = Subtarget.isPPC64(); in LowerSTACKRESTORE()
7932 bool isPPC64 = Subtarget.isPPC64(); in getReturnAddrFrameIndex()
7943 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset(); in getReturnAddrFrameIndex()
7955 bool isPPC64 = Subtarget.isPPC64(); in getFramePointerFrameIndex()
7966 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset(); in getFramePointerFrameIndex()
8001 bool isPPC64 = Subtarget.isPPC64(); in LowerEH_DWARF_CFA()
8143 if (Subtarget.isLittleEndian()) in LowerTRUNCATEVector()
8173 if (!Subtarget.hasP9Vector() && CmpVT == MVT::f128) { in LowerSELECT_CC()
8183 Subtarget.hasSPE()) in LowerSELECT_CC()
8190 if (Subtarget.hasP9Vector() && LHS == TV && RHS == FV) { in LowerSELECT_CC()
8317 const PPCSubtarget &Subtarget) { in convertFPToInt() argument
8344 if ((DestTy == MVT::i8 || DestTy == MVT::i16) && Subtarget.hasP9Vector()) in convertFPToInt()
8345 DestTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in convertFPToInt()
8351 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ); in convertFPToInt()
8354 assert((IsSigned || Subtarget.hasFPCVT()) && in convertFPToInt()
8373 SDValue Tmp = convertFPToInt(Op, DAG, Subtarget); in LowerFP_TO_INTForReuse()
8379 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() && in LowerFP_TO_INTForReuse()
8380 (IsSigned || Subtarget.hasFPCVT()); in LowerFP_TO_INTForReuse()
8405 MPI = MPI.getWithOffset(Subtarget.isLittleEndian() ? 0 : 4); in LowerFP_TO_INTForReuse()
8420 SDValue Conv = convertFPToInt(Op, DAG, Subtarget); in LowerFP_TO_INTDirectMove()
8439 return Subtarget.hasP9Vector() ? Op : SDValue(); in LowerFP_TO_INT()
8518 if (Subtarget.hasDirectMove() && Subtarget.isPPC64()) in LowerFP_TO_INT()
8546 (Subtarget.hasFPCVT() || Op.getValueType() == MVT::i32); in canReuseLoadAddress()
8622 if (!Subtarget.hasP9Vector() && in directMoveIsProfitable()
8645 const PPCSubtarget &Subtarget, in convertIntToFP() argument
8657 bool IsSingle = Op.getValueType() == MVT::f32 && Subtarget.hasFPCVT(); in convertIntToFP()
8679 assert(Subtarget.hasFPCVT() && in LowerINT_TO_FPDirectMove()
8687 return convertIntToFP(Op, Mov, DAG, Subtarget); in LowerINT_TO_FPDirectMove()
8739 if (Subtarget.isLittleEndian()) in LowerINT_TO_FPVector()
8754 if (Subtarget.hasP9Altivec()) in LowerINT_TO_FPVector()
8791 return Subtarget.hasP9Vector() ? Op : SDValue(); in LowerINT_TO_FP()
8809 if (Subtarget.hasDirectMove() && directMoveIsProfitable(Op) && in LowerINT_TO_FP()
8810 Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
8813 assert((IsSigned || Subtarget.hasFPCVT()) && in LowerINT_TO_FP()
8829 !Subtarget.hasFPCVT() && in LowerINT_TO_FP()
8874 } else if (Subtarget.hasLFIWAX() && in LowerINT_TO_FP()
8884 } else if (Subtarget.hasFPCVT() && in LowerINT_TO_FP()
8894 } else if (((Subtarget.hasLFIWAX() && in LowerINT_TO_FP()
8896 (Subtarget.hasFPCVT() && in LowerINT_TO_FP()
8931 SDValue FP = convertIntToFP(Op, Bits, DAG, Subtarget, Chain); in LowerINT_TO_FP()
8935 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
8958 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
8991 assert(Subtarget.isPPC64() && in LowerINT_TO_FP()
9013 SDValue FP = convertIntToFP(Op, Ld, DAG, Subtarget, Chain); in LowerINT_TO_FP()
9016 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
9341 if (!Subtarget.isPPC64() || (Op0.getOpcode() != ISD::BUILD_PAIR) || in LowerBITCAST()
9350 if (!Subtarget.isLittleEndian()) in LowerBITCAST()
9411 static bool isValidSplatLoad(const PPCSubtarget &Subtarget, const SDValue &Op, in isValidSplatLoad() argument
9414 if (!InputNode || !Subtarget.hasVSX() || !ISD::isUNINDEXEDLoad(InputNode)) in isValidSplatLoad()
9464 HasAnyUndefs, 0, !Subtarget.isLittleEndian()); in LowerBUILD_VECTOR()
9471 Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) { in LowerBUILD_VECTOR()
9515 isValidSplatLoad(Subtarget, Op, NewOpcode)) { in LowerBUILD_VECTOR()
9553 !Subtarget.isLittleEndian() && Subtarget.hasVSX() && in LowerBUILD_VECTOR()
9554 Subtarget.hasLFIWAX())) in LowerBUILD_VECTOR()
9562 if (NumUsesOfInputLD == 1 && Subtarget.isLittleEndian() && in LowerBUILD_VECTOR()
9563 Subtarget.isISA3_1() && ElementSize <= 16) in LowerBUILD_VECTOR()
9568 Subtarget.hasVSX()) { in LowerBUILD_VECTOR()
9588 if (Subtarget.hasVSX() && Subtarget.isPPC64() && in LowerBUILD_VECTOR()
9589 haveEfficientBuildVectorPattern(BVN, Subtarget.hasDirectMove(), in LowerBUILD_VECTOR()
9590 Subtarget.hasP8Vector())) in LowerBUILD_VECTOR()
9616 if (Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector() && SplatSize == 2) in LowerBUILD_VECTOR()
9620 if (Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector() && SplatSize == 4) in LowerBUILD_VECTOR()
9625 if (Subtarget.hasP9Vector() && SplatSize == 1) in LowerBUILD_VECTOR()
9728 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1; in LowerBUILD_VECTOR()
9734 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2; in LowerBUILD_VECTOR()
9740 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3; in LowerBUILD_VECTOR()
9831 bool IsLE = Subtarget.isLittleEndian(); in lowerToVINSERTB()
9937 bool IsLE = Subtarget.isLittleEndian(); in lowerToVINSERTH()
10076 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) || in lowerToXXSPLTI32DX()
10088 bool IsLE = Subtarget.isLittleEndian(); in lowerToXXSPLTI32DX()
10165 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerVECTOR_SHUFFLE()
10175 if (InputLoad && Subtarget.hasVSX() && V2.isUndef() && in LowerVECTOR_SHUFFLE()
10195 if ((IsFourByte && Subtarget.hasP9Vector()) || !IsFourByte) { in LowerVECTOR_SHUFFLE()
10232 if (Subtarget.hasP9Vector() && in LowerVECTOR_SHUFFLE()
10253 if (Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) { in LowerVECTOR_SHUFFLE()
10259 if (Subtarget.hasP9Altivec()) { in LowerVECTOR_SHUFFLE()
10268 if (Subtarget.hasVSX() && in LowerVECTOR_SHUFFLE()
10281 if (Subtarget.hasVSX() && in LowerVECTOR_SHUFFLE()
10294 if (Subtarget.hasP9Vector()) { in LowerVECTOR_SHUFFLE()
10314 if (Subtarget.hasVSX()) { in LowerVECTOR_SHUFFLE()
10348 (Subtarget.hasP8Altivec() && ( in LowerVECTOR_SHUFFLE()
10369 (Subtarget.hasP8Altivec() && ( in LowerVECTOR_SHUFFLE()
10448 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerVPERM()
10449 bool isPPC64 = Subtarget.isPPC64(); in LowerVPERM()
10451 if (Subtarget.hasVSX() && Subtarget.hasP9Vector() && in LowerVPERM()
10576 bool &isDot, const PPCSubtarget &Subtarget) { in getVectorCompareInfo() argument
10605 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
10617 if (Subtarget.hasP9Altivec()) { in getVectorCompareInfo()
10665 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
10684 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
10694 if (!Subtarget.isISA3_1()) in getVectorCompareInfo()
10718 if (Subtarget.hasVSX()) { in getVectorCompareInfo()
10761 if (Subtarget.hasP8Altivec()) in getVectorCompareInfo()
10772 if (Subtarget.hasP9Altivec()) in getVectorCompareInfo()
10814 if (Subtarget.hasP8Altivec()) in getVectorCompareInfo()
10829 if (Subtarget.hasP8Altivec()) in getVectorCompareInfo()
10837 if (!Subtarget.isISA3_1()) in getVectorCompareInfo()
10869 if (Subtarget.isPPC64()) in LowerINTRINSIC_WO_CHAIN()
10874 assert(Subtarget.isPPC64() && "rldimi is only available in 64-bit!"); in LowerINTRINSIC_WO_CHAIN()
10934 if (Subtarget.isISAFuture()) { in LowerINTRINSIC_WO_CHAIN()
10947 Subtarget.isLittleEndian() ? Value2 : Value, in LowerINTRINSIC_WO_CHAIN()
10948 DAG.getConstant(Subtarget.isLittleEndian() ? 1 : 0, in LowerINTRINSIC_WO_CHAIN()
10953 Subtarget.isLittleEndian() ? Value2 : Value, in LowerINTRINSIC_WO_CHAIN()
10954 DAG.getConstant(Subtarget.isLittleEndian() ? 0 : 1, in LowerINTRINSIC_WO_CHAIN()
10959 Subtarget.isLittleEndian() ? Value : Value2, in LowerINTRINSIC_WO_CHAIN()
10960 DAG.getConstant(Subtarget.isLittleEndian() ? 1 : 0, in LowerINTRINSIC_WO_CHAIN()
10965 Subtarget.isLittleEndian() ? Value : Value2, in LowerINTRINSIC_WO_CHAIN()
10966 DAG.getConstant(Subtarget.isLittleEndian() ? 0 : 1, in LowerINTRINSIC_WO_CHAIN()
10984 DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo in LowerINTRINSIC_WO_CHAIN()
10995 if (!Subtarget.isISAFuture()) in LowerINTRINSIC_WO_CHAIN()
11061 if (!Subtarget.hasVSX() || (!Subtarget.hasFloat128() && VT == MVT::f128)) in LowerINTRINSIC_WO_CHAIN()
11111 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget)) in LowerINTRINSIC_WO_CHAIN()
11186 unsigned Opcode = Subtarget.isPPC64() ? PPC::CFENCE8 : PPC::CFENCE; in LowerINTRINSIC_VOID()
11187 EVT FTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerINTRINSIC_VOID()
11203 if (!Subtarget.isPPC64()) in LowerBSWAP()
11212 if (Subtarget.isLittleEndian()) in LowerBSWAP()
11310 const PPCSubtarget &Subtarget) { in getDataClassTest() argument
11336 SDValue Rev = getDataClassTest(Op, ~Mask, Dl, DAG, Subtarget); in getDataClassTest()
11371 getDataClassTest(Op, Mask & ~fcNormal, Dl, DAG, Subtarget), Result); in getDataClassTest()
11378 SDValue NanCheck = getDataClassTest(Op, fcNan, Dl, DAG, Subtarget); in getDataClassTest()
11386 DAG.getVectorIdxConstant(Subtarget.isLittleEndian() ? 3 : 0, Dl)); in getDataClassTest()
11389 if (Subtarget.isPPC64()) { in getDataClassTest()
11398 DAG.getVectorIdxConstant(Subtarget.isLittleEndian() ? 1 : 0, Dl)); in getDataClassTest()
11415 getDataClassTest(Op, Mask & ~fcNan, Dl, DAG, Subtarget), in getDataClassTest()
11447 assert(Subtarget.hasP9Vector() && "Test data class requires Power9"); in LowerIS_FPCLASS()
11452 return getDataClassTest(LHS, Category, Dl, DAG, Subtarget); in LowerIS_FPCLASS()
11486 if (Subtarget.hasP9Vector()) { in LowerINSERT_VECTOR_ELT()
11506 if (Subtarget.isISA3_1()) { in LowerINSERT_VECTOR_ELT()
11507 if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.isPPC64()) in LowerINSERT_VECTOR_ELT()
11527 if (Subtarget.isLittleEndian()) { in LowerINSERT_VECTOR_ELT()
11550 assert((VT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorLoad()
11552 assert((VT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorLoad()
11569 if (Subtarget.isLittleEndian()) { in LowerVectorLoad()
11597 assert((StoreVT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorStore()
11599 assert((StoreVT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorStore()
11605 if (Subtarget.isISAFuture()) { in LowerVectorStore()
11617 unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx; in LowerVectorStore()
11619 if (Subtarget.isISAFuture()) { in LowerVectorStore()
11620 VecNum = Subtarget.isLittleEndian() ? 1 - (Idx % 2) : (Idx % 2); in LowerVectorStore()
11670 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerMUL()
11708 !Subtarget.hasP9Vector()) in LowerFP_ROUND()
11750 if (Subtarget.isLittleEndian()) in LowerFP_EXTEND()
11941 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64()) in ReplaceNodeResults()
12039 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in EmitAtomicBinary()
12049 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4"); in EmitAtomicBinary()
12054 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4"); in EmitAtomicBinary()
12213 const PPCInstrInfo *TII = Subtarget.getInstrInfo(); in EmitPartwordAtomicBinary()
12232 if (Subtarget.hasPartwordAtomics()) in EmitPartwordAtomicBinary()
12240 bool is64bit = Subtarget.isPPC64(); in EmitPartwordAtomicBinary()
12241 bool isLittleEndian = Subtarget.isLittleEndian(); in EmitPartwordAtomicBinary()
12426 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitEHSjLjSetJmp()
12427 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo(); in emitEHSjLjSetJmp()
12494 if (Subtarget.is64BitELFABI()) { in emitEHSjLjSetJmp()
12507 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in emitEHSjLjSetJmp()
12509 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP; in emitEHSjLjSetJmp()
12512 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW)) in emitEHSjLjSetJmp()
12535 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
12538 if (Subtarget.isPPC64()) { in emitEHSjLjSetJmp()
12568 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitEHSjLjLongJmp()
12586 : (Subtarget.isSVR4ABI() && isPositionIndependent() ? PPC::R29 in emitEHSjLjLongJmp()
12649 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) { in emitEHSjLjLongJmp()
12675 const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); in getStackProbeSize()
12698 const bool isPPC64 = Subtarget.isPPC64(); in emitProbedAlloca()
12700 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitProbedAlloca()
12900 if (Subtarget.is64BitELFABI() && in EmitInstrWithCustomInserter()
12902 !Subtarget.isUsingPCRelativeCalls()) { in EmitInstrWithCustomInserter()
12922 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in EmitInstrWithCustomInserter()
12932 if (Subtarget.hasISEL() && in EmitInstrWithCustomInserter()
13157 (Subtarget.hasPartwordAtomics() && in EmitInstrWithCustomInserter()
13159 (Subtarget.hasPartwordAtomics() && in EmitInstrWithCustomInserter()
13171 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics."); in EmitInstrWithCustomInserter()
13176 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics."); in EmitInstrWithCustomInserter()
13253 bool is64bit = Subtarget.isPPC64(); in EmitInstrWithCustomInserter()
13254 bool isLittleEndian = Subtarget.isLittleEndian(); in EmitInstrWithCustomInserter()
13530 if (Subtarget.hasDirectMove()) { in EmitInstrWithCustomInserter()
13691 static int getEstimateRefinementSteps(EVT VT, const PPCSubtarget &Subtarget) { in getEstimateRefinementSteps() argument
13696 int RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3; in getEstimateRefinementSteps()
13708 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX()))) in getSqrtInputTest()
13737 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX())) in getSqrtResultForDenormInput()
13748 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) || in getSqrtEstimate()
13749 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) || in getSqrtEstimate()
13750 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getSqrtEstimate()
13751 (VT == MVT::v2f64 && Subtarget.hasVSX())) { in getSqrtEstimate()
13753 RefinementSteps = getEstimateRefinementSteps(VT, Subtarget); in getSqrtEstimate()
13757 UseOneConstNR = !Subtarget.needsTwoConstNR(); in getSqrtEstimate()
13767 if ((VT == MVT::f32 && Subtarget.hasFRES()) || in getRecipEstimate()
13768 (VT == MVT::f64 && Subtarget.hasFRE()) || in getRecipEstimate()
13769 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRecipEstimate()
13770 (VT == MVT::v2f64 && Subtarget.hasVSX())) { in getRecipEstimate()
13772 RefinementSteps = getEstimateRefinementSteps(VT, Subtarget); in getRecipEstimate()
13789 switch (Subtarget.getCPUDirective()) { in combineRepeatedFPDivisors()
14075 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits"); in DAGCombineTruncBoolExt()
14369 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) || in DAGCombineExtBoolTrunc()
14370 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
15034 if (!Subtarget.hasVSX()) in DAGCombineBuildVector()
15057 if (Subtarget.hasP9Altivec() && !DCI.isBeforeLegalize()) { in DAGCombineBuildVector()
15066 if (Subtarget.isISA3_1()) { in DAGCombineBuildVector()
15104 SubvecIdx = Subtarget.isLittleEndian() ? 1 : 0; in DAGCombineBuildVector()
15106 SubvecIdx = Subtarget.isLittleEndian() ? 0 : 1; in DAGCombineBuildVector()
15123 if (useSoftFloat() || !Subtarget.has64BitSupport()) in combineFPToIntToFP()
15144 if (Subtarget.hasP9Vector() && Subtarget.hasP9Altivec() && SubWordLoad) { in combineFPToIntToFP()
15177 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) && in combineFPToIntToFP()
15182 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
15187 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
15194 Subtarget.hasFPCVT()) || in combineFPToIntToFP()
15212 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in combineFPToIntToFP()
15371 if (!Subtarget.hasVSX() || !Subtarget.hasFPCVT() || !isTypeLegal(ResVT)) in combineStoreFPToInt()
15376 (Op1VT == MVT::i32 || (Op1VT == MVT::i64 && Subtarget.isPPC64()) || in combineStoreFPToInt()
15377 (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); in combineStoreFPToInt()
15380 if (ResVT == MVT::ppcf128 || (ResVT == MVT::f128 && !Subtarget.hasP9Vector())) in combineStoreFPToInt()
15383 if ((Op1VT != MVT::i64 && !Subtarget.hasP8Vector()) || in combineStoreFPToInt()
15387 Val = convertFPToInt(N->getOperand(1), DAG, Subtarget); in combineStoreFPToInt()
15459 const PPCSubtarget &Subtarget) { in fixupShuffleMaskForPermutedSToV() argument
15464 Subtarget.isLittleEndian() ? HalfVec : HalfVec - ValidLaneWidth; in fixupShuffleMaskForPermutedSToV()
15474 const PPCSubtarget &Subtarget) { in getSToVPermuted() argument
15494 ResultInElt -= Subtarget.isLittleEndian() ? 0 : 1; in getSToVPermuted()
15523 bool IsLittleEndian = Subtarget.isLittleEndian(); in combineVectorShuffle()
15530 if (!Subtarget.hasDirectMove()) in combineVectorShuffle()
15592 SToVLHS = getSToVPermuted(SToVLHS, DAG, Subtarget); in combineVectorShuffle()
15602 SToVRHS = getSToVPermuted(SToVRHS, DAG, Subtarget); in combineVectorShuffle()
15614 HalfVec, ValidLaneWidth, Subtarget); in combineVectorShuffle()
15716 if (!isTypeLegal(VT) || !Subtarget.isLittleEndian() || !Subtarget.hasVSX()) in combineVReverseMemOP()
15722 if (!Subtarget.hasP9Vector()) in combineVReverseMemOP()
15879 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
15914 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine()
15935 if (Subtarget.needsSwapsForVSXMemOps() && in PerformDAGCombine()
15950 if (Subtarget.needsSwapsForVSXMemOps() && in PerformDAGCombine()
16016 if (Subtarget.isLittleEndian()) in PerformDAGCombine()
16065 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) && in PerformDAGCombine()
16067 !Subtarget.hasP8Vector() && in PerformDAGCombine()
16074 bool isLittleEndian = Subtarget.isLittleEndian(); in PerformDAGCombine()
16179 Perm = Subtarget.hasAltivec() in PerformDAGCombine()
16194 bool isLittleEndian = Subtarget.isLittleEndian(); in PerformDAGCombine()
16241 if (!DCI.isAfterLegalizeDAG() && Subtarget.hasP9Altivec() && in PerformDAGCombine()
16292 !Subtarget.isLittleEndian()); in PerformDAGCombine()
16303 if (Subtarget.needsSwapsForVSXMemOps()) in PerformDAGCombine()
16311 if (Subtarget.needsSwapsForVSXMemOps()) { in PerformDAGCombine()
16326 Subtarget.isPPC64() && N->getValueType(0) == MVT::i64; in PerformDAGCombine()
16331 (Subtarget.hasLDBRX() && Is64BitBswapOn64BitTgt))) { in PerformDAGCombine()
16383 if (Subtarget.isLittleEndian()) in PerformDAGCombine()
16523 getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) { in PerformDAGCombine()
16577 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
16661 switch (Subtarget.getCPUDirective()) { in getPrefLoopAlignment()
16687 const PPCInstrInfo *TII = Subtarget.getInstrInfo(); in getPrefLoopAlignment()
16809 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16813 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16821 if (Subtarget.hasSPE()) { in getRegForInlineAsmConstraint()
16834 if (Subtarget.hasAltivec() && VT.isVector()) in getRegForInlineAsmConstraint()
16836 else if (Subtarget.hasVSX()) in getRegForInlineAsmConstraint()
16843 } else if (Constraint == "wc" && Subtarget.useCRBits()) { in getRegForInlineAsmConstraint()
16848 Subtarget.hasVSX()) { in getRegForInlineAsmConstraint()
16853 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
16856 } else if ((Constraint == "ws" || Constraint == "ww") && Subtarget.hasVSX()) { in getRegForInlineAsmConstraint()
16857 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
16890 return Subtarget.hasSPE() in getRegForInlineAsmConstraint()
16894 return Subtarget.hasSPE() in getRegForInlineAsmConstraint()
16909 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
16922 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) { in getRegForInlineAsmConstraint()
17038 if (Ty->isVectorTy() && AM.BaseOffs != 0 && !Subtarget.hasP9Vector()) in isLegalAddressingMode()
17087 bool isPPC64 = Subtarget.isPPC64(); in LowerRETURNADDR()
17098 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl, in LowerRETURNADDR()
17143 bool isPPC64 = Subtarget.isPPC64(); in getRegisterByName()
17162 if (Subtarget.is32BitELFABI()) in isAccessedAsGotIndirect()
17167 if (Subtarget.isAIXABI()) in isAccessedAsGotIndirect()
17181 return Subtarget.isGVIndirectSymbol(G->getGlobal()); in isAccessedAsGotIndirect()
17354 if (Subtarget.hasAltivec() && Op.size() >= 16) { in getOptimalMemOpType()
17355 if (Op.isMemset() && Subtarget.hasVSX()) { in getOptimalMemOpType()
17365 if (Op.isAligned(Align(16)) || Subtarget.hasP8Vector()) in getOptimalMemOpType()
17370 if (Subtarget.isPPC64()) { in getOptimalMemOpType()
17409 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
17456 !Subtarget.allowsUnalignedFPAccess()) in allowsMisalignedMemoryAccesses()
17460 if (Subtarget.hasVSX()) { in allowsMisalignedMemoryAccesses()
17513 if (Subtarget.hasSPE() || Subtarget.useSoftFloat()) in isFMAFasterThanFMulAndFAdd()
17520 return Subtarget.hasP9Vector(); in isFMAFasterThanFMulAndFAdd()
17593 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3; in getExceptionPointerRegister()
17598 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4; in getExceptionSelectorRegister()
17605 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves in shouldExpandBuildVectorWithShuffles()
17607 if (Subtarget.hasVSX()) in shouldExpandBuildVectorWithShuffles()
17614 if (DisableILPPref || Subtarget.enableMachineScheduler()) in getSchedulingPreference()
17707 if (!Subtarget.isTargetLinux()) in useLoadStackGuardNode()
17715 if (Subtarget.isAIXABI()) { in insertSSPDeclarations()
17720 if (!Subtarget.isTargetLinux()) in insertSSPDeclarations()
17725 if (Subtarget.isAIXABI()) in getSDagStackGuard()
17732 if (!VT.isSimple() || !Subtarget.hasVSX()) in isFPImmLegal()
17742 if (Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) { in isFPImmLegal()
17801 if (!Subtarget.isISA3_0() || !Subtarget.isPPC64() || in combineSHL()
17844 const PPCSubtarget &Subtarget) { in combineADDToADDZE() argument
17845 if (!Subtarget.isPPC64()) in combineADDToADDZE()
17930 const PPCSubtarget &Subtarget) { in combineADDToMAT_PCREL_ADDR() argument
17931 if (!Subtarget.isUsingPCRelativeCalls()) in combineADDToMAT_PCREL_ADDR()
17971 if (auto Value = combineADDToADDZE(N, DCI.DAG, Subtarget)) in combineADD()
17974 if (auto Value = combineADDToMAT_PCREL_ADDR(N, DCI.DAG, Subtarget)) in combineADD()
17992 if (Subtarget.useCRBits()) { in combineTRUNCATE()
18045 switch (this->Subtarget.getCPUDirective()) { in combineMUL()
18157 if (!Subtarget.is64BitELFABI()) in mayBeEmittedAsTailCall()
18325 if (!Subtarget.hasP9Vector()) in computeMOFlags()
18330 if (Subtarget.hasPrefixInstrs()) in computeMOFlags()
18333 if (Subtarget.hasSPE()) in computeMOFlags()
18343 if (Subtarget.isISA3_1() && ((ParentOp == ISD::INTRINSIC_W_CHAIN) || in computeMOFlags()
18381 assert(Subtarget.pairedVectorMemops() && in computeMOFlags()
18465 Disp = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectForceXFormMode()
18635 assert(Subtarget.isUsingPCRelativeCalls() && in SelectOptimalAddrMode()
18686 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
18742 Disp = FI ? DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
18763 return Subtarget.isPPC64() && Subtarget.hasQuadwordAtomics(); in shouldInlineQuadwordAtomics()