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Searched refs:SubRegIndices (Results 1 – 25 of 27) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp172 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums() local
173 if (!SubRegIndices.empty()) { in runEnums()
175 std::string Namespace = SubRegIndices.front().getNamespace(); in runEnums()
180 for (const auto &Idx : SubRegIndices) in runEnums()
689 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices() local
705 std::distance(SubRegIndices.begin(), SubRegIndices.end()); in emitComposeSubRegIndices()
706 for (const auto &Idx : SubRegIndices) { in emitComposeSubRegIndices()
758 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask() local
763 for (const auto &Idx : SubRegIndices) { in emitComposeSubRegIndexLaneMask()
810 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { in emitComposeSubRegIndexLaneMask()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp121 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg()
135 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoDMR.td85 let SubRegIndices = [sub_dmrrow0, sub_dmrrow1] in {
93 let SubRegIndices = [sub_dmrrowp0, sub_dmrrowp1] in {
119 let SubRegIndices = [sub_wacc_lo, sub_wacc_hi] in {
129 let SubRegIndices = [sub_dmr0, sub_dmr1] in {
H A DPPCRegisterInfoMMA.td38 let SubRegIndices = [sub_pair0, sub_pair1] in {
63 let SubRegIndices = [sub_pair0, sub_pair1] in {
H A DPPCRegisterInfo.td45 let SubRegIndices = [sub_32];
51 let SubRegIndices = [sub_32, sub_32_hi_phony];
70 let SubRegIndices = [sub_fp0, sub_fp1];
85 let SubRegIndices = [sub_64, sub_64_hi_phony];
93 let SubRegIndices = [sub_64, sub_64_hi_phony];
125 let SubRegIndices = [sub_gp8_x0, sub_gp8_x1];
208 let SubRegIndices = [sub_vsx0, sub_vsx1] in {
279 let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h120 uint32_t SubRegIndices; member
173 const uint16_t *SubRegIndices; // Pointer to the subreg lookup variable
292 SubRegIndices = SubIndices; in InitMCRegisterInfo()
549 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; in MCSubRegIndexIterator()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp1196 for (auto &Idx : SubRegIndices) in CodeGenRegBank()
1258 for (CodeGenSubRegIndex &SRI : SubRegIndices) { in CodeGenRegBank()
1326 SubRegIndices.emplace_back(Name, Namespace, SubRegIndices.size() + 1); in createSubRegIndex()
1327 return &SubRegIndices.back(); in createSubRegIndex()
1334 SubRegIndices.emplace_back(Def, SubRegIndices.size() + 1, getHwModes()); in getSubRegIdx()
1335 Idx = &SubRegIndices.back(); in getSubRegIdx()
1509 for (const CodeGenSubRegIndex &Idx : SubRegIndices) in computeComposites()
1570 for (auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
1591 for (const auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
1610 for (auto &Idx2 : SubRegIndices) { in computeSubRegLaneMasks()
[all …]
H A DCodeGenRegisters.h585 std::deque<CodeGenSubRegIndex> SubRegIndices; variable
689 return SubRegIndices; in getSubRegIndices()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.td115 let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in {
136 let SubRegIndices = [sub_even, sub_odd], CoveredBySubRegs = 1 in
160 let SubRegIndices = [sub_vm_even, sub_vm_odd], CoveredBySubRegs = 1 in
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td46 let SubRegIndices = [sub_32];
55 let SubRegIndices = [sub_lo, sub_hi];
61 let SubRegIndices = [sub_lo, sub_hi];
68 let SubRegIndices = [sub_64];
74 let SubRegIndices = [sub_lo, sub_hi];
192 let SubRegIndices = [sub_32] in {
248 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td70 let SubRegIndices = [subreg_l32, subreg_h32];
78 let SubRegIndices = [subreg_h64, subreg_l64];
213 let SubRegIndices = [subreg_h32];
220 let SubRegIndices = [subreg_h64, subreg_l64];
256 let SubRegIndices = [subreg_h64];
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td35 let SubRegIndices = [sub_16];
45 let SubRegIndices = [sub_32];
455 let SubRegIndices = [sub_vrm1_0, sub_vrm1_1];
464 let SubRegIndices = [sub_vrm2_0, sub_vrm2_1];
473 let SubRegIndices = [sub_vrm4_0, sub_vrm4_1];
577 let SubRegIndices = [sub_gpr_even, sub_gpr_odd];
589 let SubRegIndices = [sub_gpr_even, sub_gpr_odd];
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td37 let SubRegIndices = [sub_32];
43 let SubRegIndices = [sub_64];
49 let SubRegIndices = [sub_128];
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td186 let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
192 let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {
201 let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {
212 let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {
234 let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {
247 let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {
259 let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {
280 let SubRegIndices = [sub_32bit] in {
383 let SubRegIndices = [sub_xmm], PositionOrder = 1 in {
389 let SubRegIndices
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td136 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
168 let SubRegIndices = [subreg_overflow];
205 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
231 let SubRegIndices = [vsub_lo, vsub_hi, vsub_fake], CoveredBySubRegs = 1 in {
251 let SubRegIndices = [vsub_lo, vsub_hi, vsub_fake], CoveredBySubRegs = 1 in {
271 let SubRegIndices = [wsub_lo, wsub_hi], CoveredBySubRegs = 1 in {
372 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
451 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td28 let SubRegIndices = [sub_32];
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td30 let SubRegIndices = [sub_32] in {
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td169 let SubRegIndices = [lo16, hi16];
199 let SubRegIndices = [sub0, sub1];
208 let SubRegIndices = [sub0, sub1];
238 let SubRegIndices = [sub0, sub1];
262 let SubRegIndices = [sub0, sub1];
291 let SubRegIndices = [sub0, sub1];
301 let SubRegIndices = [sub0, sub1];
310 let SubRegIndices = [sub0, sub1];
329 let SubRegIndices = [sub0, sub1];
511 let SubRegIndices = indices;
H A DR600RegisterInfo.td23 let SubRegIndices = [sub0, sub1, sub2, sub3];
32 let SubRegIndices = [sub0, sub1];
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td35 let SubRegIndices = [sub32_0];
43 let SubRegIndices = [sub64_0];
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.td54 let SubRegIndices = [subreg_8bit] in {
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td101 let SubRegIndices = [sub_32] in {
312 let SubRegIndices = [bsub] in {
347 let SubRegIndices = [hsub] in {
382 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in {
417 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
837 let SubRegIndices = [psub] in {
857 let SubRegIndices = [zsub] in {
1623 let SubRegIndices = [zasubq0, zasubq1] in {
1634 let SubRegIndices = [zasubd0, zasubd1] in {
1641 let SubRegIndices = [zasubs0, zasubs1] in {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td43 let SubRegIndices = [sub_even, sub_odd];
52 let SubRegIndices = [sub_even, sub_odd];
59 let SubRegIndices = [sub_even64, sub_odd64];
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td23 let SubRegIndices = SUBIDX;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td120 let SubRegIndices = [ssub_0, ssub_1] in {
158 let SubRegIndices = [dsub_0, dsub_1] in {
168 let SubRegIndices = [dsub_0, dsub_1] in {

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