| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 405 ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal); in lowerInlineAsm() local
406 assert(SrcRegs.size() == 1 && "Single register is expected here"); in lowerInlineAsm()
409 Register In = SrcRegs[0]; in lowerInlineAsm()
413 if (!buildAnyextOrCopy(In, SrcRegs[0], MIRBuilder)) in lowerInlineAsm()
|
| H A D | CallLowering.cpp | 327 ArrayRef<Register> SrcRegs) { in mergeVectorRegsToResultRegs() argument
330 LLT PartLLT = MRI.getType(SrcRegs[0]); in mergeVectorRegsToResultRegs()
337 return B.buildConcatVectors(DstRegs[0], SrcRegs); in mergeVectorRegsToResultRegs()
346 DstRegs[0], B.buildMergeLikeInstr(LCMTy, SrcRegs)); in mergeVectorRegsToResultRegs()
350 assert(SrcRegs.size() == 1); in mergeVectorRegsToResultRegs()
351 UnmergeSrcReg = SrcRegs[0]; in mergeVectorRegsToResultRegs()
|
| H A D | LegalizerHelper.cpp | 1753 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); in narrowScalar() local
1759 SrcRegs[i / 2], MIRBuilder, MRI); in narrowScalar()
1768 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); in narrowScalar()
1946 SmallVector<Register, 2> SrcRegs; in narrowScalar() local
1952 SrcRegs.push_back(SrcReg); in narrowScalar()
1956 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1)); in narrowScalar()
1967 DstRegs.push_back(SrcRegs[i]); in narrowScalar()
1985 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) in narrowScalar()
2003 SmallVector<Register, 2> SrcRegs, DstRegs; in narrowScalar() local
2005 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs, in narrowScalar()
[all …]
|
| H A D | IRTranslator.cpp | 1491 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateExtractValue() local
1497 DstRegs[i] = SrcRegs[Idx++]; in translateExtractValue()
1508 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateInsertValue() local
1516 DstRegs[i] = SrcRegs[i]; in translateInsertValue()
1704 SmallVector<Register, 3> SrcRegs; in translateMemFunc() local
1712 SrcRegs.push_back(SrcReg); in translateMemFunc()
1718 Register &SizeOpReg = SrcRegs[SrcRegs.size() - 1]; in translateMemFunc()
1723 for (Register SrcReg : SrcRegs) in translateMemFunc()
3479 const ArrayRef<Register> SrcRegs = getOrCreateVRegs(*U.getOperand(0)); in translateFreeze() local
3481 assert(DstRegs.size() == SrcRegs.size() && in translateFreeze()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 1137 Register SrcRegs[] = {0, 0}; in LowerPATCHABLE_EVENT_CALL() local
1148 SrcRegs[I] = getX86SubSuperRegister(Op.getReg(), 64); in LowerPATCHABLE_EVENT_CALL()
1149 assert(SrcRegs[I].isValid() && "Invalid operand"); in LowerPATCHABLE_EVENT_CALL()
1150 if (SrcRegs[I] != DestRegs[I]) { in LowerPATCHABLE_EVENT_CALL()
1164 if (SrcRegs[I] != DestRegs[I]) in LowerPATCHABLE_EVENT_CALL()
1166 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); in LowerPATCHABLE_EVENT_CALL()
1237 Register SrcRegs[] = {0, 0, 0}; in LowerPATCHABLE_TYPED_EVENT_CALL() local
1248 SrcRegs[I] = getX86SubSuperRegister(Op.getReg(), 64); in LowerPATCHABLE_TYPED_EVENT_CALL()
1249 assert(SrcRegs[I].isValid() && "Invalid operand"); in LowerPATCHABLE_TYPED_EVENT_CALL()
1250 if (SrcRegs[I] != DestRegs[I]) { in LowerPATCHABLE_TYPED_EVENT_CALL()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 1095 const SmallVectorImpl<RegSubRegPair> &SrcRegs, in insertPHI() argument
1097 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?"); in insertPHI()
1099 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
1102 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
1109 for (const RegSubRegPair &RegPair : SrcRegs) { in insertPHI()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 1004 SmallSet<std::pair<Register, unsigned>, 4> SrcRegs; in needToBeConvertedToVALU() local
1013 SrcRegs.insert(std::pair(SiblingCopy->getOperand(1).getReg(), in needToBeConvertedToVALU()
1017 Info->SiblingPenalty = SrcRegs.size(); in needToBeConvertedToVALU()
|
| H A D | AMDGPURegisterBankInfo.cpp | 1138 SmallVector<Register, 1> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingLoad() local
1140 if (SrcRegs.empty()) in applyMappingLoad()
1141 SrcRegs.push_back(MI.getOperand(1).getReg()); in applyMappingLoad()
1145 Register BasePtrReg = SrcRegs[0]; in applyMappingLoad()
2658 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingImpl() local
2659 if (SrcRegs.empty()) in applyMappingImpl()
2676 B.buildFreeze(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
2678 auto Freeze = B.buildFreeze(S32, SrcRegs[0]); in applyMappingImpl()
2687 B.buildCopy(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
2740 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingImpl() local
[all …]
|
| H A D | AMDGPULegalizerInfo.cpp | 2856 SmallVector<Register, 8> SrcRegs; in legalizeInsertVectorElt() local
2858 SrcRegs.push_back(MRI.createGenericVirtualRegister(EltTy)); in legalizeInsertVectorElt()
2859 B.buildUnmerge(SrcRegs, Vec); in legalizeInsertVectorElt()
2861 SrcRegs[IdxVal] = MI.getOperand(2).getReg(); in legalizeInsertVectorElt()
2862 B.buildMergeLikeInstr(Dst, SrcRegs); in legalizeInsertVectorElt()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 327 SmallVector<Register, 8> SrcRegs(NumSrcs); in tryCombineTrunc()
329 SrcRegs[i] = SrcMerge->getSourceReg(i); in tryCombineTrunc()
331 Builder.buildMergeValues(DstReg, SrcRegs); in tryCombineTrunc()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInstructionSelector.cpp | 134 MachineInstr &I, std::vector<Register> SrcRegs,
|