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Searched refs:SrcReg2 (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp179 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare() argument
187 SrcReg2 = Register(); in analyzeCompare()
193 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
207 unsigned SrcReg2, int64_t ImmValue, in isRedundantFlagInstr() argument
212 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
213 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
285 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, in optimizeCompareInstr() argument
306 if (SrcReg2 != 0) in optimizeCompareInstr()
332 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
384 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
H A DLanaiInstrInfo.h99 Register &SrcReg2, int64_t &CmpMask,
106 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp250 MCRegister SrcReg2 = MI.getOperand(1).getReg(); in expandLongCondBr() local
260 SrcReg2.id() == RISCV::X0) { in expandLongCondBr()
262 } else if (RISCV::X8 <= SrcReg2.id() && SrcReg2.id() <= RISCV::X15 && in expandLongCondBr()
264 std::swap(SrcReg1, SrcReg2); in expandLongCondBr()
280 MCInstBuilder(InvOpc).addReg(SrcReg1).addReg(SrcReg2).addImm(8); in expandLongCondBr()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp613 Register SrcReg2 = in fuseCompareOperations() local
618 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) in fuseCompareOperations()
676 if (SrcReg2) in fuseCompareOperations()
677 MBBI->clearRegisterKills(SrcReg2, TRI); in fuseCompareOperations()
H A DSystemZInstrInfo.h248 Register &SrcReg2, int64_t &Mask,
H A DSystemZInstrInfo.cpp534 Register &SrcReg2, int64_t &Mask, in analyzeCompare() argument
541 SrcReg2 = 0; in analyzeCompare()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp854 unsigned SrcReg2 = 0; in PPCEmitCmp() local
856 SrcReg2 = getRegForValue(SrcValue2); in PPCEmitCmp()
857 if (SrcReg2 == 0) in PPCEmitCmp()
865 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr; in PPCEmitCmp()
888 SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2); in PPCEmitCmp()
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
940 SrcReg2 = ExtReg; in PPCEmitCmp()
946 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
1358 Register SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1359 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
[all …]
H A DPPCInstrInfo.h547 Register &SrcReg2, int64_t &Mask,
551 Register SrcReg2, int64_t Mask, int64_t Value,
H A DPPCInstrInfo.cpp2348 Register &SrcReg2, int64_t &Mask, in analyzeCompare() argument
2359 SrcReg2 = 0; in analyzeCompare()
2370 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
2378 Register SrcReg2, int64_t Mask, in optimizeCompareInstr() argument
2485 if (SrcReg2 != 0) in optimizeCompareInstr()
2565 Instr.getOperand(2).getReg() == SrcReg2) || in optimizeCompareInstr()
2566 (Instr.getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
2620 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
2767 Register SrcReg, SrcReg2; in optimizeCmpPostRA() local
2769 if (!analyzeCompare(CmpMI, SrcReg, SrcReg2, CmpMask, CmpValue)) in optimizeCmpPostRA()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h563 Register &SrcReg2, int64_t &CmpMask,
570 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
715 Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
H A DX86InstrInfo.cpp1431 Register SrcReg, SrcReg2; in convertToThreeAddress() local
1573 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/false, SrcReg2, isKill2, in convertToThreeAddress()
1583 SrcReg = SrcReg2; in convertToThreeAddress()
1596 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); in convertToThreeAddress()
1600 if (SrcReg2 != Src2.getReg()) in convertToThreeAddress()
1601 LV->getVarInfo(SrcReg2).Kills.push_back(NewMI); in convertToThreeAddress()
1602 if (SrcReg != SrcReg2 && SrcReg != Src.getReg()) in convertToThreeAddress()
2039 if (SrcReg2) in convertToThreeAddress()
2040 LIS->getInterval(SrcReg2); in convertToThreeAddress()
4766 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1415 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1417 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1418 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1426 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1427 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1434 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1436 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1763 Register SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1764 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
H A DARMBaseInstrInfo.cpp2789 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare() argument
2797 SrcReg2 = 0; in analyzeCompare()
2805 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
2812 SrcReg2 = 0; in analyzeCompare()
2860 Register SrcReg, Register SrcReg2, in isRedundantFlagInstr() argument
2867 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
2868 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
2876 OI->getOperand(3).getReg() == SrcReg2) || in isRedundantFlagInstr()
2877 (OI->getOperand(2).getReg() == SrcReg2 && in isRedundantFlagInstr()
2904 OI->getOperand(1).getReg() == SrcReg2) { in isRedundantFlagInstr()
[all …]
H A DARMBaseInstrInfo.h297 Register &SrcReg2, int64_t &CmpMask,
305 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp562 Register DstReg, Register SrcReg1, Register SrcReg2) { in matchPushAddSubExt() argument
575 LLT Ext2SrcTy = MRI.getType(SrcReg2); in matchPushAddSubExt()
588 Register SrcReg1, Register SrcReg2) { in applyPushAddSubExt() argument
593 Register Ext2Reg = B.buildInstr(Opc, {MidTy}, {SrcReg2}).getReg(0); in applyPushAddSubExt()
H A DAArch64LegalizerInfo.cpp1410 Register SrcReg2 = MI.getOperand(3).getReg(); in legalizeICMP() local
1427 .buildICmp(CmpInst::ICMP_EQ, MRI.getType(DstReg), SrcReg1, SrcReg2) in legalizeICMP()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp442 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement()
448 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
451 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
441 Register SrcReg2 = MI.getOperand(3).getReg(); optimizeVectElement() local
H A DAArch64InstrInfo.h420 Register &SrcReg2, int64_t &CmpMask,
425 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
H A DAArch64InstrInfo.cpp1175 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare() argument
1189 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
1208 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
1217 SrcReg2 = 0; in analyzeCompare()
1226 SrcReg2 = 0; in analyzeCompare()
1536 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, in optimizeCompareInstr() argument
1565 return optimizePTestInstr(&CmpInstr, SrcReg, SrcReg2, MRI); in optimizeCompareInstr()
1567 if (SrcReg2 != 0) in optimizeCompareInstr()
6673 Register SrcReg2; in genFusedMultiply() local
6677 SrcReg2 = *ReplacedAddend; in genFusedMultiply()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp670 Register SrcReg, SrcReg2; in optimizeCmpInstr() local
672 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
673 SrcReg.isPhysical() || SrcReg2.isPhysical()) in optimizeCmpInstr()
678 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { in optimizeCmpInstr()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h274 Register &SrcReg2, int64_t &Mask,
H A DHexagonInstrInfo.cpp1881 Register &SrcReg2, int64_t &Mask, in analyzeCompare() argument
1942 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
1958 SrcReg2 = 0; in analyzeCompare()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1713 Register &SrcReg2, int64_t &Mask, in analyzeCompare() argument
1722 Register SrcReg2, int64_t Mask, in optimizeCompareInstr() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h381 Register &SrcReg2, int64_t &CmpMask,
385 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
H A DSIInstrInfo.cpp9708 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare() argument
9734 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
9737 SrcReg2 = Register(); in analyzeCompare()
9757 SrcReg2 = Register(); in analyzeCompare()
9767 Register SrcReg2, int64_t CmpMask, in optimizeCompareInstr() argument
9773 if (SrcReg2 && !getFoldableImm(SrcReg2, *MRI, CmpValue)) in optimizeCompareInstr()