Lines Matching refs:SrcReg2
1415 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1417 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1418 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1426 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1427 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1434 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1436 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1763 Register SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1764 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
1771 .addReg(SrcReg1).addReg(SrcReg2)); in SelectBinaryIntOp()