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Searched refs:SrcIdx (Results 1 – 25 of 27) sorted by relevance

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/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGNonTrivialStruct.cpp33 enum { DstIdx = 0, SrcIdx = 1 }; enumerator
518 Address SrcAddr = this->getAddrWithOffset(Addrs[SrcIdx], this->Start); in flushTrivialFields()
556 Address SrcAddr = this->getAddrWithOffset(Addrs[SrcIdx], Offset); in visitVolatileTrivial()
563 Address SrcAddr = Addrs[SrcIdx].withElementType(Ty); in visitVolatileTrivial()
680 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], CurStructOffset, FD); in visitARCStrong()
682 Addrs[SrcIdx], QT.isVolatileQualified(), QT, SourceLocation()); in visitARCStrong()
690 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], CurStructOffset, FD); in visitARCWeak()
691 CGF->EmitARCCopyWeak(Addrs[DstIdx], Addrs[SrcIdx]); in visitARCWeak()
697 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], Offset); in callSpecialFunction()
699 CGF->MakeAddrLValue(Addrs[SrcIdx], FT)); in callSpecialFunction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp1453 static unsigned getSrcIdx(const MachineInstr* MI, unsigned SrcIdx) { in getSrcIdx() argument
1456 ++SrcIdx; in getSrcIdx()
1459 ++SrcIdx; in getSrcIdx()
1462 return SrcIdx; in getSrcIdx()
1614 unsigned SrcIdx = getSrcIdx(MI, 1); in printZeroUpperMove() local
1618 printDstRegisterName(CS, MI, SrcIdx); in printZeroUpperMove()
1621 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx)) { in printZeroUpperMove()
1640 unsigned SrcIdx = getSrcIdx(MI, 1); in printBroadcast() local
1641 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx)) { in printBroadcast()
1644 printDstRegisterName(CS, MI, SrcIdx); in printBroadcast()
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H A DX86InstrInfo.cpp2433 unsigned SrcIdx = (Imm >> 6) & 3; in commuteInstructionImpl() local
2437 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 && in commuteInstructionImpl()
7230 unsigned SrcIdx = (Imm >> 6) & 3; in foldMemoryOperandCustom() local
7237 int PtrOffset = SrcIdx * 4; in foldMemoryOperandCustom()
H A DX86ISelLowering.cpp5679 unsigned SrcIdx = M / Size; in getTargetShuffleAndZeroables() local
5719 if (IsSrcConstant[SrcIdx]) { in getTargetShuffleAndZeroables()
5720 if (UndefSrcElts[SrcIdx][M]) in getTargetShuffleAndZeroables()
5722 else if (SrcEltBits[SrcIdx][M] == 0) in getTargetShuffleAndZeroables()
6058 unsigned SrcIdx = SrcExtract.getConstantOperandVal(1); in getFauxShuffleMask() local
6059 unsigned SrcByte = SrcIdx * (SrcVT.getScalarSizeInBits() / 8); in getFauxShuffleMask()
6463 uint64_t SrcIdx = Op.getConstantOperandVal(1); in getShuffleScalarElt() local
6464 return getShuffleScalarElt(Src, Index + SrcIdx, DAG, Depth + 1); in getShuffleScalarElt()
11917 int SrcIdx = i + Offset; in lowerShuffleAsSpecificZeroOrAnyExtend() local
11918 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1; in lowerShuffleAsSpecificZeroOrAnyExtend()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelperVectorOps.cpp331 int SrcIdx = Mask[Offset]; in matchExtractVectorElementWithShuffleVector() local
343 if (SrcIdx < 0 && in matchExtractVectorElementWithShuffleVector()
350 if (SrcIdx < 0) in matchExtractVectorElementWithShuffleVector()
356 if (SrcIdx < (int)LHSWidth) { in matchExtractVectorElementWithShuffleVector()
361 SrcIdx -= LHSWidth; in matchExtractVectorElementWithShuffleVector()
375 auto Idx = B.buildConstant(IdxTy, SrcIdx); in matchExtractVectorElementWithShuffleVector()
H A DUtils.cpp1005 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) { in ConstantFoldCountZeros() local
1006 if (auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) { in ConstantFoldCountZeros()
1487 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) { in isConstantOrConstantVector() local
1488 if (getIConstantVRegValWithLookThrough(BV->getSourceReg(SrcIdx), MRI) || in isConstantOrConstantVector()
1489 getOpcodeDef<GImplicitDef>(BV->getSourceReg(SrcIdx), MRI)) in isConstantOrConstantVector()
H A DCombinerHelper.cpp2170 unsigned SrcIdx = MI.getNumOperands() - 1; in matchCombineUnmergeConstant() local
2171 Register SrcReg = MI.getOperand(SrcIdx).getReg(); in matchCombineUnmergeConstant()
2185 for (unsigned Idx = 0; Idx != SrcIdx; ++Idx) { in matchCombineUnmergeConstant()
2210 unsigned SrcIdx = MI.getNumOperands() - 1; in matchCombineUnmergeUndef() local
2211 Register SrcReg = MI.getOperand(SrcIdx).getReg(); in matchCombineUnmergeUndef()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterCoalescer.h42 unsigned SrcIdx = 0; variable
106 unsigned getSrcIdx() const { return SrcIdx; } in getSrcIdx()
H A DTwoAddressInstructionPass.cpp171 unsigned SrcIdx, unsigned DstIdx,
1314 unsigned SrcIdx, unsigned DstIdx, unsigned &Dist, bool shouldOnlyCommute) { in tryInstructionTransform() argument
1320 Register regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1328 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1354 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1519 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { in collectTiedOperands() local
1521 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1524 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands()
1546 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); in collectTiedOperands()
1567 unsigned SrcIdx = TP.first; in processTiedPairs() local
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H A DRegisterCoalescer.cpp454 SrcIdx = DstIdx = 0; in setRegisters()
502 SrcIdx, DstIdx); in setRegisters()
507 SrcIdx = DstSub; in setRegisters()
524 if (DstIdx && !SrcIdx) { in setRegisters()
526 std::swap(SrcIdx, DstIdx); in setRegisters()
544 std::swap(SrcIdx, DstIdx); in flip()
569 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
583 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
1292 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx(); in reMaterializeTrivialDef() local
1339 if (SrcIdx && DstIdx) in reMaterializeTrivialDef()
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H A DPeepholeOptimizer.cpp1919 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast() local
1920 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1929 if (SrcIdx != EndOpIdx) in getNextSourceFromBitcast()
1932 SrcIdx = OpIdx; in getNextSourceFromBitcast()
1937 if (SrcIdx >= Def->getNumOperands()) in getNextSourceFromBitcast()
1947 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
H A DTargetRegisterInfo.cpp389 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
392 SrcIdx, DefIdx) != nullptr; in shareSameRegisterFile()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp500 unsigned PredIdx, DOPIdx, SrcIdx, Src2Idx; in expand_DestructiveOp() local
507 std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(1, 3, 2); in expand_DestructiveOp()
514 std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(1, 2, 3); in expand_DestructiveOp()
517 std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(2, 3, 3); in expand_DestructiveOp()
520 std::tie(PredIdx, DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 2, 3, 4); in expand_DestructiveOp()
523 std::tie(PredIdx, DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 3, 4, 2); in expand_DestructiveOp()
527 std::tie(PredIdx, DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 4, 3, 2); in expand_DestructiveOp()
541 DOPRegIsUnique = DstReg != MI.getOperand(SrcIdx).getReg(); in expand_DestructiveOp()
547 MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg(); in expand_DestructiveOp()
556 (MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg() && in expand_DestructiveOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h111 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
309 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
H A DR600InstrInfo.cpp233 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx()
249 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { in getSelIdx()
292 int SrcIdx = getOperandIdx(MI.getOpcode(), Op[0]); in getSrcs() local
293 if (SrcIdx < 0) in getSrcs()
295 MachineOperand &MO = MI.getOperand(SrcIdx); in getSrcs()
1372 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp() argument
1394 switch (SrcIdx) { in getFlagOp()
1411 switch (SrcIdx) { in getFlagOp()
H A DR600ISelLowering.h110 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
H A DAMDGPUInstCombineIntrinsic.cpp1369 for (unsigned SrcIdx = 0; SrcIdx < 4; ++SrcIdx) { in simplifyAMDGCNMemoryIntrinsicDemanded() local
1370 const unsigned Bit = 1 << SrcIdx; in simplifyAMDGCNMemoryIntrinsicDemanded()
H A DSIFoldOperands.cpp251 unsigned SrcIdx = ~0; in tryFoldImmWithOpSel() local
254 SrcIdx = 0; in tryFoldImmWithOpSel()
257 SrcIdx = 1; in tryFoldImmWithOpSel()
260 SrcIdx = 2; in tryFoldImmWithOpSel()
335 if (SrcIdx == 1 && (IsUAdd || IsUSub)) { in tryFoldImmWithOpSel()
H A DR600ISelLowering.cpp1943 bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx, in FoldOperand() argument
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DInferAddressSpaces.cpp1268 int SrcIdx = U.getOperandNo(); in rewriteWithNewAddressSpaces() local
1269 int OtherIdx = (SrcIdx == 0) ? 1 : 0; in rewriteWithNewAddressSpaces()
1275 Cmp->setOperand(SrcIdx, NewV); in rewriteWithNewAddressSpaces()
1283 Cmp->setOperand(SrcIdx, NewV); in rewriteWithNewAddressSpaces()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h689 for (unsigned SrcIdx = StartSrcIdx; SrcIdx < StartSrcIdx + NumSrcsUsed; in findValueFromBuildVector() local
690 ++SrcIdx) in findValueFromBuildVector()
691 NewSrcs.push_back(BV.getReg(SrcIdx)); in findValueFromBuildVector()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp549 int SrcIdx = in visitExtractElementInst() local
555 if (SrcIdx < 0) in visitExtractElementInst()
557 if (SrcIdx < (int)LHSWidth) in visitExtractElementInst()
560 SrcIdx -= LHSWidth; in visitExtractElementInst()
565 Src, ConstantInt::get(Int64Ty, SrcIdx, false)); in visitExtractElementInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4350 auto SrcIdx = getNamedOperandIdx(Opcode, SrcName); in validateLdsDirect() local
4351 if (SrcIdx == -1) in validateLdsDirect()
4353 const auto &Src = Inst.getOperand(SrcIdx); in validateLdsDirect()
7021 int SrcIdx = 0; in cvtExp() local
7028 assert(SrcIdx < 4); in cvtExp()
7029 OperandIdx[SrcIdx] = Inst.size(); in cvtExp()
7031 ++SrcIdx; in cvtExp()
7036 assert(SrcIdx < 4); in cvtExp()
7037 OperandIdx[SrcIdx] = Inst.size(); in cvtExp()
7039 ++SrcIdx; in cvtExp()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
H A DInstrRefBasedImpl.cpp2127 LocIdx SrcIdx = MTracker->getSpillMLoc(SpillID); in transferSpillOrRestoreInst() local
2128 auto ReadValue = MTracker->readMLoc(SrcIdx); in transferSpillOrRestoreInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp862 SmallVectorImpl<int> &SrcIdx) { in buildHvxVectorReg()
866 SrcIdx.push_back(-1); in buildHvxVectorReg()
881 SrcIdx.push_back(I); in buildHvxVectorReg()
863 __anona938eeb30302(SDValue &SrcVec, SmallVectorImpl<int> &SrcIdx) buildHvxVectorReg() argument

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