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Searched refs:Src1Reg (Results 1 – 18 of 18) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
318 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
320 if (HexagonMCInstrInfo::isIntReg(Src1Reg) && in getDuplexCandidateGroup()
322 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) { in getDuplexCandidateGroup()
326 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup()
334 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
336 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup()
353 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
355 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup()
363 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
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H A DHexagonMCCompound.cpp81 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
98 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
101 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getCompoundCandidateGroup()
143 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
145 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getCompoundCandidateGroup()
157 Src1Reg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
158 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg) in getCompoundCandidateGroup()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp104 Register Src1Reg = MBBI->getOperand(1).getReg(); in selectSELRMux() local
107 bool Src1IsHigh = SystemZ::isHighReg(Src1Reg); in selectSELRMux()
113 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
119 Src1Reg = DestReg; in selectSELRMux()
132 if (DestReg != Src1Reg && DestReg == Src2Reg) { in selectSELRMux()
134 std::swap(Src1Reg, Src2Reg); in selectSELRMux()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp692 Register Src1Reg = MI.getOperand(1).getReg(); in matchDupLane() local
693 const LLT SrcTy = MRI.getType(Src1Reg); in matchDupLane()
748 Register Src1Reg = MI.getOperand(1).getReg(); in applyDupLane() local
749 const LLT SrcTy = MRI.getType(Src1Reg); in applyDupLane()
760 {Src1Reg, Undef.getReg(0)}) in applyDupLane()
769 Register Src1Reg = Unmerge.getReg(Unmerge.getNumOperands() - 1); in matchScalarizeVectorUnmerge() local
770 const LLT SrcTy = MRI.getType(Src1Reg); in matchScalarizeVectorUnmerge()
780 Register Src1Reg = Unmerge.getReg(Unmerge.getNumOperands() - 1); in applyScalarizeVectorUnmerge() local
781 const LLT SrcTy = MRI.getType(Src1Reg); in applyScalarizeVectorUnmerge()
786 B.buildExtractVectorElementConstant(Unmerge.getReg(I), Src1Reg, I); in applyScalarizeVectorUnmerge()
H A DAArch64InstructionSelector.cpp1896 Register Src1Reg = I.getOperand(1).getReg(); in selectVectorSHL() local
1926 auto Shl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg}); in selectVectorSHL()
1942 Register Src1Reg = I.getOperand(1).getReg(); in selectVectorAshrLshr() local
1989 auto SShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Neg}); in selectVectorAshrLshr()
3801 Register Src1Reg = I.getOperand(1).getReg(); in selectMergeValues() local
3804 MachineInstr *InsMI = emitLaneInsert(std::nullopt, Tmp.getReg(0), Src1Reg, in selectMergeValues()
5065 Register Src1Reg = I.getOperand(1).getReg(); in selectShuffleVector() local
5066 const LLT Src1Ty = MRI.getType(Src1Reg); in selectShuffleVector()
5108 emitVectorConcat(std::nullopt, Src1Reg, Src2Reg, MIB); in selectShuffleVector()
5133 SmallVector<Register, 2> Regs = {Src1Reg, Src2Reg}; in selectShuffleVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1288 Register Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
1290 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1291 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1312 Register Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
1315 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1316 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); in expandPostRAPseudo()
3427 Register DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
3442 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
3446 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg)) in getCompoundCandidateGroup()
3479 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp275 Register Src1Reg = MI->getOperand(2).getReg(); in ExpandFPMLxInstruction() local
291 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h623 Register Src1Reg = Concat.getSourceReg(0); in findValueFromConcat() local
624 unsigned SrcSize = MRI.getType(Src1Reg).getSizeInBits(); in findValueFromConcat()
655 Register Src1Reg = BV.getSourceReg(0); in findValueFromBuildVector() local
656 unsigned SrcSize = MRI.getType(Src1Reg).getSizeInBits(); in findValueFromBuildVector()
679 LLT SrcTy = MRI.getType(Src1Reg); in findValueFromBuildVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1038 Register Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
1042 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1060 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg); in selectSelect()
1933 Register Src1Reg = getRegForValue(I->getOperand(1)); in selectDivRem() local
1934 if (!Src0Reg || !Src1Reg) in selectDivRem()
1937 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
1938 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2656 Register Src1Reg = getRegForValue(Src1Val); in optimizeSelect() local
2657 if (!Src1Reg) in optimizeSelect()
2665 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, 1); in optimizeSelect()
2667 Register ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, in optimizeSelect()
2779 Register Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
2782 if (!Src1Reg || !Src2Reg) in selectSelect()
2786 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, ExtraCC); in selectSelect()
2788 Register ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, CC); in selectSelect()
4639 Register Src1Reg = getRegForValue(I->getOperand(1)); in selectRem() local
4640 if (!Src1Reg) in selectRem()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h270 unsigned Src1Reg = 0) const;
H A DR600InstrInfo.cpp1214 unsigned Src1Reg) const { in buildDefaultInstruction()
1218 if (Src1Reg) { in buildDefaultInstruction()
1232 if (Src1Reg) { in buildDefaultInstruction()
1233 MIB.addReg(Src1Reg) // $src1 in buildDefaultInstruction()
H A DAMDGPUInstructionSelector.cpp437 Register Src1Reg = I.getOperand(3).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local
462 !RBI.constrainGenericRegister(Src1Reg, AMDGPU::SReg_32RegClass, *MRI)) in selectG_UADDO_USUBO_UADDE_USUBE()
791 Register Src1Reg = I.getOperand(2).getReg(); in selectG_INSERT() local
792 LLT Src1Ty = MRI->getType(Src1Reg); in selectG_INSERT()
818 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI); in selectG_INSERT()
832 !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI)) in selectG_INSERT()
838 .addReg(Src1Reg) in selectG_INSERT()
1027 Register Src1Reg = I.getOperand(3).getReg(); in selectG_INTRINSIC() local
1031 for (Register Reg : { DstReg, Src0Reg, Src1Reg }) in selectG_INTRINSIC()
1379 Register Src1Reg = in selectIntrinsicCmp() local
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H A DAMDGPULegalizerInfo.cpp2481 Register Src1Reg = MI.getOperand(2).getReg(); in legalizeFrem() local
2485 auto Div = B.buildFDiv(Ty, Src0Reg, Src1Reg, Flags); in legalizeFrem()
2488 B.buildFMA(DstReg, Neg, Src1Reg, Src0Reg, Flags); in legalizeFrem()
H A DAMDGPURegisterBankInfo.cpp4611 Register Src1Reg = MI.getOperand(3).getReg(); in getInstrMapping() local
4613 unsigned Src1Size = MRI.getType(Src1Reg).getSizeInBits(); in getInstrMapping()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1850 auto [DstReg, DstTy, Src1Reg, Src1Ty] = MI.getFirst2RegLLTs(); in widenScalarMergeValues()
1854 LLT SrcTy = MRI.getType(Src1Reg); in widenScalarMergeValues()
1866 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1Reg).getReg(0); in widenScalarMergeValues()
4911 auto [DstReg, DstTy, Src1Reg, Src1Ty, Src2Reg, Src2Ty] = in fewerElementsVectorShuffle()
4930 extractParts(Src1Reg, NarrowTy, 2, SplitSrc1Regs, MIRBuilder, MRI); in fewerElementsVectorShuffle()
7600 auto [DstReg, DstTy, Src0Reg, Src0Ty, Src1Reg, Src1Ty] = in lowerShuffleVector()
7618 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); in lowerShuffleVector()
7621 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector()
H A DCombinerHelper.cpp4674 Register Src1Reg = PtrAdd.getBaseReg(); in reassociationCanBreakAddressingModePattern() local
4675 auto *Src1Def = getOpcodeDef<GPtrAdd>(Src1Reg, MRI); in reassociationCanBreakAddressingModePattern()
4681 if (MRI.hasOneNonDBGUse(Src1Reg)) in reassociationCanBreakAddressingModePattern()
4739 Register Src1Reg = MI.getOperand(1).getReg(); in matchReassocConstantInnerRHS() local
4750 Builder.buildPtrAdd(PtrTy, Src1Reg, RHS->getOperand(1).getReg()); in matchReassocConstantInnerRHS()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp18258 Register Src1Reg = MI.getOperand(1).getReg(); in emitQuietFCMP()
18268 .addReg(Src1Reg) in emitQuietFCMP()
18279 .addReg(Src1Reg, getKillRegState(MI.getOperand(1).isKill())) in emitQuietFCMP()
18255 Register Src1Reg = MI.getOperand(1).getReg(); emitQuietFCMP() local