Lines Matching refs:Src1Reg
2656 Register Src1Reg = getRegForValue(Src1Val); in optimizeSelect() local
2657 if (!Src1Reg) in optimizeSelect()
2665 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, 1); in optimizeSelect()
2667 Register ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, in optimizeSelect()
2779 Register Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
2782 if (!Src1Reg || !Src2Reg) in selectSelect()
2786 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, ExtraCC); in selectSelect()
2788 Register ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, CC); in selectSelect()
4639 Register Src1Reg = getRegForValue(I->getOperand(1)); in selectRem() local
4640 if (!Src1Reg) in selectRem()
4645 Register QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, Src1Reg); in selectRem()
4649 Register ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, Src1Reg, Src0Reg); in selectRem()
4711 Register Src1Reg = getRegForValue(I->getOperand(1)); in selectMul() local
4712 if (!Src1Reg) in selectMul()
4715 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src1Reg); in selectMul()