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Searched refs:SimpleTy (Results 1 – 25 of 69) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h53 SimpleValueType SimpleTy = INVALID_SIMPLE_VALUE_TYPE; variable
56 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} in MVT()
58 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
59 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
60 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
61 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
62 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
63 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
73 return (SimpleTy >= MVT::FIRST_VALUETYPE && in isValid()
74 SimpleTy <= MVT::LAST_VALUETYPE); in isValid()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h48 if (V.SimpleTy != VT.V.SimpleTy)
50 if (V.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
66 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getIntegerVT()
76 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
85 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getVectorVT()
137 return V.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE; in isSimple()
499 return V.SimpleTy; in getRawBits()
508 if (L.V.SimpleTy == R.V.SimpleTy) in operator()
511 return L.V.SimpleTy < R.V.SimpleTy; in operator()
H A DTargetLowering.h1028 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1049 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; in getRepRegClassFor()
1056 return RepRegClassCostForVT[VT.SimpleTy]; in getRepRegClassCostFor()
1079 (unsigned)VT.getSimpleVT().SimpleTy < std::size(RegClassForVT)); in isTypeLegal()
1080 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr; in isTypeLegal()
1095 return ValueTypeActions[VT.SimpleTy]; in getTypeAction()
1099 ValueTypeActions[VT.SimpleTy] = Action; in setTypeAction()
1261 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op]; in getOperationAction()
1442 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getLoadExtAction()
1443 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getLoadExtAction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp144 if (LocVT.SimpleTy == MVT::i64 || (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32)) in CC_AArch64_Custom_Block()
146 else if (LocVT.SimpleTy == MVT::f16) in CC_AArch64_Custom_Block()
148 else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector()) in CC_AArch64_Custom_Block()
150 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
152 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
179 unsigned EltsPerReg = (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32) ? 2 : 1; in CC_AArch64_Custom_Block()
H A DAArch64FastISel.cpp321 switch (VT.SimpleTy) { in getImplicitScaleFactor()
1170 switch (RetVT.SimpleTy) { in emitAddSub()
1189 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1474 switch (VT.SimpleTy) { in emitCmp()
1651 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); in emitLogicalOp()
1672 switch (RetVT.SimpleTy) { in emitLogicalOp_ri()
1722 switch (RetVT.SimpleTy) { in emitLogicalOp_rs()
1829 switch (VT.SimpleTy) { in emitLoad()
2059 switch (VT.SimpleTy) { in emitStoreRelease()
2118 switch (VT.SimpleTy) { in emitStore()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp891 switch (VT.getSimpleVT().SimpleTy) { in getLdStRegType()
977 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy; in tryLoad()
1127 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1134 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_avar, in tryLoadVector()
1152 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1159 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_asi, in tryLoadVector()
1179 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1186 EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_ari_64, in tryLoadVector()
1196 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1203 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_ari, in tryLoadVector()
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H A DNVPTXTargetTransformInfo.cpp419 if (LT.second.SimpleTy == MVT::i64) in simplifyNvvmIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp162 switch (V.SimpleTy) { in getEVTString()
205 switch (V.SimpleTy) { in getTypeForEVT()
300 if (SimpleTy == INVALID_SIMPLE_VALUE_TYPE) in print()
H A DTargetLoweringBase.cpp491 switch (VT.SimpleTy) { \ in getSYNC()
670 OpActions[(unsigned)VT.SimpleTy][NT] = Expand; in initActions()
928 assert((unsigned)SVT.SimpleTy < std::size(TransformToType)); in getTypeConversion()
929 MVT NVT = TransformToType[SVT.SimpleTy]; in getTypeConversion()
1226 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1502 return getPointerTy(DL).SimpleTy; in getSetCCResultType()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenDAGPatterns.h87 return (Words[T.SimpleTy / WordWidth] >> (T.SimpleTy % WordWidth)) & 1; in count()
90 bool V = count(T.SimpleTy); in insert()
91 Words[T.SimpleTy / WordWidth] |= WordType(1) << (T.SimpleTy % WordWidth); in insert()
101 Words[T.SimpleTy / WordWidth] &= ~(WordType(1) << (T.SimpleTy % WordWidth)); in erase()
703 return Types[ResNo].getMachineValueType().SimpleTy; in getSimpleType()
H A DInfoByHwMode.cpp78 StringRef N = llvm::getEnumName(T.SimpleTy); in getMVTName()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp225 auto isHvxTy = [this, IncludeBool](MVT SimpleTy) { in isTypeForHVX() argument
226 if (isHVXVectorType(SimpleTy, IncludeBool)) in isTypeForHVX()
228 auto Action = getTargetLowering()->getPreferredVectorAction(SimpleTy); in isTypeForHVX()
237 MVT SimpleTy = MVT::getVectorVT(ElemTy, VecLen); in isTypeForHVX() local
238 if (SimpleTy.isValid() && isHvxTy(SimpleTy)) in isTypeForHVX()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp334 switch (VT.SimpleTy) { in X86FastEmitLoad()
491 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
663 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
1364 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode()
1386 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode()
1557 switch (SrcVT.SimpleTy) { in X86SelectZExt()
1725 switch (SourceVT.SimpleTy) { in X86SelectBranch()
1924 switch (VT.SimpleTy) { in X86SelectDivRem()
2253 switch (RetVT.SimpleTy) { in X86FastEmitSSESelect()
2276 switch (RetVT.SimpleTy) { in X86FastEmitPseudoSelect()
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H A DX86ISelDAGToDAG.cpp3611 switch (MemVT.getSimpleVT().SimpleTy) { in foldLoadStoreIntoMemOperand()
4837 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
4843 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
4848 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
5407 switch (NVT.SimpleTy) { in Select()
5544 switch (NVT.SimpleTy) { in Select()
5626 switch (NVT.SimpleTy) { in Select()
5748 switch (NVT.SimpleTy) { in Select()
5756 switch (NVT.SimpleTy) { in Select()
5767 switch (NVT.SimpleTy) { in Select()
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp232 MVT MT1 = VT1.getSimpleVT().SimpleTy; in isZExtFree()
233 MVT MT2 = VT2.getSimpleVT().SimpleTy; in isZExtFree()
352 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments() local
353 switch (SimpleTy) { in LowerFormalArguments()
365 SimpleTy == MVT::i64 ? &BPF::GPRRegClass : &BPF::GPR32RegClass); in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp41 switch (Type.SimpleTy) { in toValType()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.cpp87 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp159 switch (VT.SimpleTy) { in selectIndexedLoad()
203 if (VT.SimpleTy == MVT::i8 && Offs == 1 && Bank == 0) in selectIndexedProgMemLoad()
412 switch (VT.SimpleTy) { in select()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp315 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
341 switch (VT.SimpleTy) { in tryIndexedLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp802 switch (VT.SimpleTy) { in ARMSimplifyAddress()
858 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) in AddLoadStoreOperands()
905 switch (VT.SimpleTy) { in ARMEmitLoad()
1044 switch (VT.SimpleTy) { in ARMEmitStore()
1381 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1815 Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp()
1908 switch (ArgVT.SimpleTy) { in ProcessCallArgs()
3047 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
H A DARMCallingConv.cpp198 switch (LocVT.SimpleTy) { in CC_ARM_AAPCS_Custom_Aggregate()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp757 switch (VT.SimpleTy) { in emitLoad()
811 switch (VT.SimpleTy) { in emitStore()
1365 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
1826 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1844 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1870 switch (SrcVT.SimpleTy) { in emitIntZExt()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelMatcherGen.cpp40 VT = VVT.getSimple().SimpleTy; in getRegisterValueType()
47 assert(VVT.isSimple() && VVT.getSimple().SimpleTy == VT && in getRegisterValueType()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp524 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
527 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp832 assert((VT.SimpleTy == MVT::v16i8 || VT.SimpleTy == MVT::v8i16 || in lower128BitShuffle()
833 VT.SimpleTy == MVT::v4i32 || VT.SimpleTy == MVT::v2i64 || in lower128BitShuffle()
834 VT.SimpleTy == MVT::v4f32 || VT.SimpleTy == MVT::v2f64) && in lower128BitShuffle()
1257 assert((VT.SimpleTy == MVT::v32i8 || VT.SimpleTy == MVT::v16i16 || in lower256BitShuffle()
1258 VT.SimpleTy == MVT::v8i32 || VT.SimpleTy == MVT::v4i64 || in lower256BitShuffle()
1259 VT.SimpleTy == MVT::v8f32 || VT.SimpleTy == MVT::v4f64) && in lower256BitShuffle()
5808 switch (VT.getSimpleVT().SimpleTy) { in isFMAFasterThanFMulAndFAdd()

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