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Searched refs:SimpleTy (Results 1 – 25 of 69) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h56 SimpleValueType SimpleTy = INVALID_SIMPLE_VALUE_TYPE; variable
59 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} in MVT()
61 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
62 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
63 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
64 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
65 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
66 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
76 return (SimpleTy >= MVT::FIRST_VALUETYPE && in isValid()
77 SimpleTy <= MVT::LAST_VALUETYPE); in isValid()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h49 if (V.SimpleTy != VT.V.SimpleTy)
51 if (V.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
67 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getIntegerVT()
77 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
86 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getVectorVT()
138 return V.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE; in isSimple()
509 return V.SimpleTy; in getRawBits()
518 if (L.V.SimpleTy == R.V.SimpleTy) in operator()
521 return L.V.SimpleTy < R.V.SimpleTy; in operator()
H A DTargetLowering.h1058 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1079 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; in getRepRegClassFor()
1086 return RepRegClassCostForVT[VT.SimpleTy]; in getRepRegClassCostFor()
1109 (unsigned)VT.getSimpleVT().SimpleTy < std::size(RegClassForVT)); in isTypeLegal()
1110 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr; in isTypeLegal()
1122 return ValueTypeActions[VT.SimpleTy]; in getTypeAction()
1126 ValueTypeActions[VT.SimpleTy] = Action; in setTypeAction()
1291 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op]; in getOperationAction()
1472 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getLoadExtAction()
1473 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getLoadExtAction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp143 if (LocVT.SimpleTy == MVT::i64 || (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32)) in CC_AArch64_Custom_Block()
145 else if (LocVT.SimpleTy == MVT::f16 || LocVT.SimpleTy == MVT::bf16) in CC_AArch64_Custom_Block()
147 else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector()) in CC_AArch64_Custom_Block()
149 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
151 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
178 unsigned EltsPerReg = (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32) ? 2 : 1; in CC_AArch64_Custom_Block()
H A DAArch64FastISel.cpp315 switch (VT.SimpleTy) { in getImplicitScaleFactor()
1165 switch (RetVT.SimpleTy) { in emitAddSub()
1184 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1469 switch (VT.SimpleTy) { in emitCmp()
1648 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); in emitLogicalOp()
1669 switch (RetVT.SimpleTy) { in emitLogicalOp_ri()
1719 switch (RetVT.SimpleTy) { in emitLogicalOp_rs()
1825 switch (VT.SimpleTy) { in emitLoad()
2055 switch (VT.SimpleTy) { in emitStoreRelease()
2114 switch (VT.SimpleTy) { in emitStore()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenDAGPatterns.h84 assert(T.SimpleTy < Capacity && "Capacity needs to be enlarged"); in count()
85 return (Words[T.SimpleTy / WordWidth] >> (T.SimpleTy % WordWidth)) & 1; in count()
88 assert(T.SimpleTy < Capacity && "Capacity needs to be enlarged"); in insert()
89 bool V = count(T.SimpleTy); in insert()
90 Words[T.SimpleTy / WordWidth] |= WordType(1) << (T.SimpleTy % WordWidth); in insert()
100 assert(T.SimpleTy < Capacity && "Capacity needs to be enlarged"); in erase()
101 Words[T.SimpleTy / WordWidth] &= ~(WordType(1) << (T.SimpleTy % WordWidth)); in erase()
702 return Types[ResNo].getMachineValueType().SimpleTy; in getSimpleType()
H A DInfoByHwMode.cpp80 StringRef N = llvm::getEnumName(T.SimpleTy); in getMVTName()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp163 switch (V.SimpleTy) { in getEVTString()
218 switch (V.SimpleTy) { in getTypeForEVT()
318 switch (getScalarType().SimpleTy) { in getFltSemantics()
342 if (SimpleTy == INVALID_SIMPLE_VALUE_TYPE) in print()
H A DTargetLoweringBase.cpp526 switch (VT.SimpleTy) { \ in getSYNC()
750 OpActions[(unsigned)VT.SimpleTy][NT] = Expand; in initActions()
1027 assert((unsigned)SVT.SimpleTy < std::size(TransformToType)); in getTypeConversion()
1028 MVT NVT = TransformToType[SVT.SimpleTy]; in getTypeConversion()
1325 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1601 return getPointerTy(DL).SimpleTy; in getSetCCResultType()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp224 auto isHvxTy = [this, IncludeBool](MVT SimpleTy) { in isTypeForHVX() argument
225 if (isHVXVectorType(SimpleTy, IncludeBool)) in isTypeForHVX()
227 auto Action = getTargetLowering()->getPreferredVectorAction(SimpleTy); in isTypeForHVX()
236 MVT SimpleTy = MVT::getVectorVT(ElemTy, VecLen); in isTypeForHVX() local
237 if (SimpleTy.isValid() && isHvxTy(SimpleTy)) in isTypeForHVX()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp1059 const MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy; in tryLoad()
1147 pickOpcodeForVT(EltVT.SimpleTy, NVPTX::LDV_i8_v2, NVPTX::LDV_i16_v2, in tryLoadVector()
1152 pickOpcodeForVT(EltVT.SimpleTy, NVPTX::LDV_i8_v4, NVPTX::LDV_i16_v4, in tryLoadVector()
1156 Opcode = pickOpcodeForVT(EltVT.SimpleTy, {/* no v8i8 */}, {/* no v8i16 */}, in tryLoadVector()
1206 const MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy; in tryLDG()
1259 MVT::getIntegerVT(LD->getMemoryVT().getSizeInBits() / NumElts).SimpleTy; in tryLDU()
1344 pickOpcodeForVT(Value.getSimpleValueType().SimpleTy, NVPTX::ST_i8, in tryStore()
1399 ST->getOperand(1).getSimpleValueType().SimpleTy; in tryStoreVector()
1461 Opcode = pickOpcodeForVT(MemVT.getSimpleVT().SimpleTy, in tryLoadParam()
1467 pickOpcodeForVT(MemVT.getSimpleVT().SimpleTy, NVPTX::LoadParamMemV2I8, in tryLoadParam()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp335 switch (VT.SimpleTy) { in X86FastEmitLoad()
492 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
664 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
1363 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode()
1385 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode()
1558 switch (SrcVT.SimpleTy) { in X86SelectZExt()
1726 switch (SourceVT.SimpleTy) { in X86SelectBranch()
1930 switch (VT.SimpleTy) { in X86SelectDivRem()
2259 switch (RetVT.SimpleTy) { in X86FastEmitSSESelect()
2282 switch (RetVT.SimpleTy) { in X86FastEmitPseudoSelect()
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H A DX86ISelDAGToDAG.cpp279 switch (VT.SimpleTy) { in getAddressOperands()
3677 switch (MemVT.getSimpleVT().SimpleTy) { in foldLoadStoreIntoMemOperand()
4905 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
4911 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
4916 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
5564 switch (NVT.SimpleTy) { in Select()
5701 switch (NVT.SimpleTy) { in Select()
5783 switch (NVT.SimpleTy) { in Select()
5905 switch (NVT.SimpleTy) { in Select()
5913 switch (NVT.SimpleTy) { in Select()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSDNodeInfoEmitter.cpp228 StringRef VTName = VT.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE in emitTypeConstraint()
230 : getEnumName(VT.SimpleTy); in emitTypeConstraint()
H A DDAGISelMatcherGen.cpp40 VT = VVT.getSimple().SimpleTy; in getRegisterValueType()
47 assert(VVT.isSimple() && VVT.getSimple().SimpleTy == VT && in getRegisterValueType()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp41 switch (Type.SimpleTy) { in toValType()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp240 MVT MT1 = VT1.getSimpleVT().SimpleTy; in isZExtFree()
241 MVT MT2 = VT2.getSimpleVT().SimpleTy; in isZExtFree()
368 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments() local
369 switch (SimpleTy) { in LowerFormalArguments()
381 SimpleTy == MVT::i64 ? &BPF::GPRRegClass : &BPF::GPR32RegClass); in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.cpp87 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp159 switch (VT.SimpleTy) { in selectIndexedLoad()
203 if (VT.SimpleTy == MVT::i8 && Offs == 1 && Bank == 0) in selectIndexedProgMemLoad()
412 switch (VT.SimpleTy) { in select()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp311 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
337 switch (VT.SimpleTy) { in tryIndexedLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp835 switch (VT.SimpleTy) { in ARMSimplifyAddress()
891 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) in AddLoadStoreOperands()
940 switch (VT.SimpleTy) { in ARMEmitLoad()
1082 switch (VT.SimpleTy) { in ARMEmitStore()
1425 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1877 Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp()
1970 switch (ArgVT.SimpleTy) { in ProcessCallArgs()
3117 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
H A DARMCallingConv.cpp198 switch (LocVT.SimpleTy) { in CC_ARM_AAPCS_Custom_Aggregate()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp755 switch (VT.SimpleTy) { in emitLoad()
809 switch (VT.SimpleTy) { in emitStore()
1377 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
1838 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1856 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1882 switch (SrcVT.SimpleTy) { in emitIntZExt()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp507 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
510 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp898 switch (ResTy.getSimpleVT().SimpleTy) { in lowerBITREVERSE()
1726 assert((VT.SimpleTy == MVT::v16i8 || VT.SimpleTy == MVT::v8i16 || in lower128BitShuffle()
1727 VT.SimpleTy == MVT::v4i32 || VT.SimpleTy == MVT::v2i64 || in lower128BitShuffle()
1728 VT.SimpleTy == MVT::v4f32 || VT.SimpleTy == MVT::v2f64) && in lower128BitShuffle()
1767 if ((VT.SimpleTy == MVT::v2i64 || VT.SimpleTy == MVT::v2f64) && in lower128BitShuffle()
2212 assert((VT.SimpleTy == MVT::v32i8 || VT.SimpleTy == MVT::v16i16 || in lower256BitShuffle()
2213 VT.SimpleTy == MVT::v8i32 || VT.SimpleTy == MVT::v4i64 || in lower256BitShuffle()
2214 VT.SimpleTy == MVT::v8f32 || VT.SimpleTy == MVT::v4f64) && in lower256BitShuffle()
4674 switch (SrcVT.getSimpleVT().SimpleTy) { in performBITCASTCombine()
8021 switch (VT.getSimpleVT().SimpleTy) { in isFMAFasterThanFMulAndFAdd()

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