Searched refs:SiFive7 (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVSchedSiFive7.td | 1 //==- RISCVSchedSiFive7.td - SiFive7 Scheduling Definitions --*- tablegen -*-=//
12 /// On the SiFive7, the worst case LMUL is the Largest LMUL
20 /// MxList. On the SiFive7, the worst case LMUL is the Largest LMUL
111 // FIXME: On SiFive7, VLEN is 512. Although a user can request the compiler
195 // SiFive7 machine model for scheduling and other instruction cost heuristics.
197 let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order.
209 // The SiFive7 microarchitecture has three pipelines: A, B, V.
490 defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS8", VLDSX0Pred, [SiFive7VCQ, SiFive7VL],
510 defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS16", VLDSX0Pred, [SiFive7VCQ, SiFive7VL],
527 defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS32", VLDSX0Pred, [SiFive7VCQ, SiFive7VL],
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| H A D | RISCVSubtarget.h | 64 SiFive7, enumerator
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| H A D | RISCVFeatures.td | 1372 def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
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