Lines Matching refs:SiFive7
1 //==- RISCVSchedSiFive7.td - SiFive7 Scheduling Definitions --*- tablegen -*-=//
12 /// On the SiFive7, the worst case LMUL is the Largest LMUL
20 /// MxList. On the SiFive7, the worst case LMUL is the Largest LMUL
111 // FIXME: On SiFive7, VLEN is 512. Although a user can request the compiler
195 // SiFive7 machine model for scheduling and other instruction cost heuristics.
197 let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order.
209 // The SiFive7 microarchitecture has three pipelines: A, B, V.
490 defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS8", VLDSX0Pred, [SiFive7VCQ, SiFive7VL],
510 defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS16", VLDSX0Pred, [SiFive7VCQ, SiFive7VL],
527 defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS32", VLDSX0Pred, [SiFive7VCQ, SiFive7VL],
544 defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS64", VLDSX0Pred, [SiFive7VCQ, SiFive7VL],