| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 901 ARM_AM::ShiftOpc ShiftTy; member
911 ARM_AM::ShiftOpc ShiftTy; member
918 ARM_AM::ShiftOpc ShiftTy; member
1481 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; in isPostIdxReg()
2612 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
2623 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); in addRegShiftedImmOperands()
3364 PostIdxReg.ShiftTy); in addPostIdxRegShiftedOperands()
3721 Op->RegShiftedReg.ShiftTy = ShTy; in CreateShiftedRegister()
3735 Op->RegShiftedImm.ShiftTy = ShTy; in CreateShiftedImmediate()
3911 CreatePostIdxReg(MCRegister Reg, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2093 LLT ShiftTy = MRI.getType(MI.getOperand(0).getReg()); in applyCombineMulToShl() local
2094 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
2098 if (ShiftVal == ShiftTy.getScalarSizeInBits() - 1) in applyCombineMulToShl()
2639 static LLT getMidVTForTruncRightShiftCombine(LLT ShiftTy, LLT TruncTy) { in getMidVTForTruncRightShiftCombine() argument
2640 const unsigned ShiftSize = ShiftTy.getScalarSizeInBits(); in getMidVTForTruncRightShiftCombine()
2645 return ShiftTy.changeElementSize(32); in getMidVTForTruncRightShiftCombine()
2653 return ShiftTy; in getMidVTForTruncRightShiftCombine()
7070 LLT ShiftTy = TrueTy.isVector() ? TrueTy.getElementType() : TrueTy; in tryFoldSelectOfConstants() local
7071 auto ShAmtC = B.buildConstant(ShiftTy, TrueValue.exactLogBase2()); in tryFoldSelectOfConstants()
7086 LLT ShiftTy = TrueTy.isVector() ? TrueTy.getElementType() : TrueTy; in tryFoldSelectOfConstants() local
[all …]
|
| H A D | LegalizerHelper.cpp | 2427 LLT ShiftTy = SrcTy; in widenScalarExtract() local
2430 ShiftTy = WideTy; in widenScalarExtract()
2434 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); in widenScalarExtract()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 832 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult() argument
844 DAG.getConstant(C.logBase2(), DL, ShiftTy)); in genConstMult()
855 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult()
856 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
862 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); in genConstMult()
863 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 206 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2838 ARM_AM::ShiftOpc ShiftTy) { in SelectShift() argument
2884 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
2887 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); in SelectShift()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1490 LLT ShiftTy = MRI.getType(ShiftNo); in legalizeFunnelShift() local
1496 APInt BitWidth(ShiftTy.getSizeInBits(), OperationTy.getSizeInBits(), false); in legalizeFunnelShift()
1509 if (ShiftTy.getSizeInBits() == 64 && MI.getOpcode() == TargetOpcode::G_FSHR && in legalizeFunnelShift()
|
| H A D | AArch64InstructionSelector.cpp | 3213 const LLT ShiftTy = MRI.getType(ShiftReg); in select() local
3216 ShiftTy.getSizeInBits() == 64) { in select()
3217 assert(!ShiftTy.isVector() && "unexpected vector shift ty"); in select()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 3644 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local
3649 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift()
3650 assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(Op1.getValueSizeInBits()) && in visitShift()
3652 Op2 = DAG.getZExtOrTrunc(Op2, getCurSDLoc(), ShiftTy); in visitShift()
6019 EVT ShiftTy = TLI.getShiftAmountTy(PromVT, DAG.getDataLayout()); in expandDivFix() local
6024 DAG.getConstant(1, DL, ShiftTy)); in expandDivFix()
6028 DAG.getConstant(1, DL, ShiftTy)); in expandDivFix()
|
| H A D | LegalizeIntegerTypes.cpp | 4988 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandIntRes_Shift() local
4989 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
4990 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 5741 auto *ShiftTy = FixedVectorType::get( in getArithmeticReductionCost() local
5744 Instruction::LShr, ShiftTy, CostKind, in getArithmeticReductionCost()
5920 auto *ShiftTy = FixedVectorType::get( in getMinMaxReductionCost() local
5923 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, in getMinMaxReductionCost()
|
| H A D | X86ISelLowering.cpp | 52594 EVT ShiftTy = Shift.getValueType(); in foldXorTruncShiftIntoCmp() local
52595 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64) in foldXorTruncShiftIntoCmp()
52600 Shift.getConstantOperandAPInt(1) != (ShiftTy.getSizeInBits() - 1)) in foldXorTruncShiftIntoCmp()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SVEInstrInfo.td | 1863 …multiclass adrShiftPat<ValueType Ty, ValueType PredTy, ValueType ShiftTy, Instruction DestAdrIns, …
1867 (Ty (splat_vector (ShiftTy ShiftAmt)))))),
|