| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 901 ARM_AM::ShiftOpc ShiftTy; member
911 ARM_AM::ShiftOpc ShiftTy; member
918 ARM_AM::ShiftOpc ShiftTy; member
1480 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; in isPostIdxReg()
2611 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
2622 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); in addRegShiftedImmOperands()
3363 PostIdxReg.ShiftTy); in addPostIdxRegShiftedOperands()
3720 Op->RegShiftedReg.ShiftTy = ShTy; in CreateShiftedRegister()
3734 Op->RegShiftedImm.ShiftTy = ShTy; in CreateShiftedImmediate()
3906 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 793 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult() argument
805 DAG.getConstant(C.logBase2(), DL, ShiftTy)); in genConstMult()
816 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult()
817 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
823 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); in genConstMult()
824 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 181 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2771 ARM_AM::ShiftOpc ShiftTy) { in SelectShift() argument
2814 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
2817 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); in SelectShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1363 LLT ShiftTy = MRI.getType(ShiftNo); in legalizeFunnelShift() local
1369 APInt BitWidth(ShiftTy.getSizeInBits(), OperationTy.getSizeInBits(), false); in legalizeFunnelShift()
1382 if (ShiftTy.getSizeInBits() == 64 && MI.getOpcode() == TargetOpcode::G_FSHR && in legalizeFunnelShift()
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| H A D | AArch64InstructionSelector.cpp | 3078 const LLT ShiftTy = MRI.getType(ShiftReg); in select() local
3081 ShiftTy.getSizeInBits() == 64) { in select()
3082 assert(!ShiftTy.isVector() && "unexpected vector shift ty"); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2024 LLT ShiftTy = MRI.getType(MI.getOperand(0).getReg()); in applyCombineMulToShl() local
2025 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
2619 static LLT getMidVTForTruncRightShiftCombine(LLT ShiftTy, LLT TruncTy) { in getMidVTForTruncRightShiftCombine() argument
2620 const unsigned ShiftSize = ShiftTy.getScalarSizeInBits(); in getMidVTForTruncRightShiftCombine()
2625 return ShiftTy.changeElementSize(32); in getMidVTForTruncRightShiftCombine()
2633 return ShiftTy; in getMidVTForTruncRightShiftCombine()
6778 LLT ShiftTy = TrueTy.isVector() ? TrueTy.getElementType() : TrueTy; in tryFoldSelectOfConstants() local
6779 auto ShAmtC = B.buildConstant(ShiftTy, TrueValue.exactLogBase2()); in tryFoldSelectOfConstants()
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| H A D | LegalizerHelper.cpp | 2129 LLT ShiftTy = SrcTy; in widenScalarExtract() local
2132 ShiftTy = WideTy; in widenScalarExtract()
2136 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); in widenScalarExtract()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 3592 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local
3597 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift()
3598 assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(Op1.getValueSizeInBits()) && in visitShift()
3600 Op2 = DAG.getZExtOrTrunc(Op2, getCurSDLoc(), ShiftTy); in visitShift()
5925 EVT ShiftTy = TLI.getShiftAmountTy(PromVT, DAG.getDataLayout()); in expandDivFix() local
5930 DAG.getConstant(1, DL, ShiftTy)); in expandDivFix()
5934 DAG.getConstant(1, DL, ShiftTy)); in expandDivFix()
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| H A D | LegalizeIntegerTypes.cpp | 4748 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandIntRes_Shift() local
4749 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
4750 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 5407 auto *ShiftTy = FixedVectorType::get( in getArithmeticReductionCost() local
5410 Instruction::LShr, ShiftTy, CostKind, in getArithmeticReductionCost()
5586 auto *ShiftTy = FixedVectorType::get( in getMinMaxReductionCost() local
5589 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, in getMinMaxReductionCost()
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| H A D | X86ISelLowering.cpp | 50868 EVT ShiftTy = Shift.getValueType(); in foldXorTruncShiftIntoCmp() local
50869 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64) in foldXorTruncShiftIntoCmp()
50874 Shift.getConstantOperandAPInt(1) != (ShiftTy.getSizeInBits() - 1)) in foldXorTruncShiftIntoCmp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SVEInstrInfo.td | 1742 …multiclass adrShiftPat<ValueType Ty, ValueType PredTy, ValueType ShiftTy, Instruction DestAdrIns, …
1746 (Ty (splat_vector (ShiftTy ShiftAmt)))))),
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