901     ARM_AM::ShiftOpc ShiftTy;  member
911     ARM_AM::ShiftOpc ShiftTy;  member
918     ARM_AM::ShiftOpc ShiftTy;  member
1480     return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;  in isPostIdxReg()
2611       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));  in addRegShiftedRegOperands()
2622       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));  in addRegShiftedImmOperands()
3363                                      PostIdxReg.ShiftTy);  in addPostIdxRegShiftedOperands()
3720     Op->RegShiftedReg.ShiftTy = ShTy;  in CreateShiftedRegister()
3734     Op->RegShiftedImm.ShiftTy = ShTy;  in CreateShiftedImmediate()
3906   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,  in CreatePostIdxReg()  argument
3911     Op->PostIdxReg.ShiftTy = ShiftTy;  in CreatePostIdxReg()
4053     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)  in print()
4054       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "  in print()
4076        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "  in print()
4081        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"  in print()
4303   auto ShiftTy = ShiftTyOpt.value();  in tryParseShiftRegister()  local
4319   if (ShiftTy == ARM_AM::rrx) {  in tryParseShiftRegister()
4346           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||  in tryParseShiftRegister()
4347           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {  in tryParseShiftRegister()
4354         ShiftTy = ARM_AM::lsl;  in tryParseShiftRegister()
4370   if (ShiftReg && ShiftTy != ARM_AM::rrx)  in tryParseShiftRegister()
4372         ShiftTy, SrcReg, ShiftReg, Imm, S, EndLoc, *this));  in tryParseShiftRegister()
4374     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,  in tryParseShiftRegister()
5684   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;  in parsePostIdxReg()  local
5688     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))  in parsePostIdxReg()
5696       ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, ShiftImm, S, E, *this));  in parsePostIdxReg()
10494     ARM_AM::ShiftOpc ShiftTy;  in processInstruction()  local
10497     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;  in processInstruction()
10498     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;  in processInstruction()
10499     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;  in processInstruction()
10500     case ARM::RORr: ShiftTy = ARM_AM::ror; break;  in processInstruction()
10502     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);  in processInstruction()
10519     ARM_AM::ShiftOpc ShiftTy;  in processInstruction()  local
10522     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;  in processInstruction()
10523     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;  in processInstruction()
10524     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;  in processInstruction()
10525     case ARM::RORi: ShiftTy = ARM_AM::ror; break;  in processInstruction()
10531     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))  in processInstruction()
10533     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);  in processInstruction()