| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 27 enum ShiftOpc { enum
44 inline const StringRef getShiftOpcStr(ShiftOpc Op) { in getShiftOpcStr()
56 inline unsigned getShiftOpcEncoding(ShiftOpc Op) { in getShiftOpcEncoding()
98 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc()
102 inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7); } in getSORegShOp()
400 inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
412 inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { in getAM2ShiftOpc()
413 return (ShiftOpc)((AM2Opc >> 13) & 7); in getAM2ShiftOpc()
|
| H A D | ARMMCCodeEmitter.cpp | 248 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
257 llvm_unreachable("Invalid ShiftOpc!"); in getShiftOp()
1280 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1318 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue()
1533 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
1578 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getSORegImmOpValue()
1687 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getT2SORegOpValue()
|
| H A D | ARMInstPrinter.cpp | 52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift()
436 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMSelectionDAGInfo.h | 23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode()
|
| H A D | ARMInstructionSelector.cpp | 62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
806 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc, in selectShift() argument
810 MIB.addImm(ShiftOpc); in selectShift()
1071 return selectShift(ARM_AM::ShiftOpc::lsr, MIB); in select()
1073 return selectShift(ARM_AM::ShiftOpc::asr, MIB); in select()
1075 return selectShift(ARM_AM::ShiftOpc::lsl, MIB); in select()
|
| H A D | ARMFastISel.cpp | 181 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2698 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; in ARMEmitIntExt()
2725 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; in ARMEmitIntExt()
2771 ARM_AM::ShiftOpc ShiftTy) { in SelectShift()
|
| H A D | ARMISelDAGToDAG.cpp | 90 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
550 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
623 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectImmShifterOperand()
647 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectRegShifterOperand()
769 ARM_AM::ShiftOpc ShOpcVal = in SelectLdStSOReg()
849 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectAddrMode2OffsetReg()
1516 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg()
3381 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL); in tryV6T2BitfieldExtractOp()
|
| H A D | ARMBaseInstrInfo.cpp | 236 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress()
|
| H A D | ARMISelLowering.cpp | 19822 ARM_AM::ShiftOpc ShOpcVal= in getARMIndexedAddressParts()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 798 unsigned ShiftOpc = Left ? S2_asl_i_r in splitShift() local
836 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR)) in splitShift()
853 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR) in splitShift()
882 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR)) in splitShift()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 447 std::optional<ARM_AM::ShiftOpc> tryParseShiftToken();
455 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
635 ParseStatus parsePKHImm(OperandVector &O, ARM_AM::ShiftOpc, int Low,
891 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
901 ARM_AM::ShiftOpc ShiftTy;
911 ARM_AM::ShiftOpc ShiftTy;
918 ARM_AM::ShiftOpc ShiftTy;
3716 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedRegister()
3730 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedImmediate()
3888 ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, in CreateMem()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineShifts.cpp | 1123 auto ShiftOpc = ShrAmtC > ShAmtC ? Shr->getOpcode() : Instruction::Shl; in visitShl() local
1129 Value *NewShift = Builder.CreateBinOp(ShiftOpc, X, ShiftDiffC, "sh.diff"); in visitShl()
|
| H A D | InstCombineCompares.cpp | 7549 unsigned ShiftOpc = ShiftI->getOpcode(); in visitICmpInst() local
7550 if ((ExtOpc == Instruction::ZExt && ShiftOpc == Instruction::LShr) || in visitICmpInst()
7551 (ExtOpc == Instruction::SExt && ShiftOpc == Instruction::AShr)) { in visitICmpInst()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1147 EVT VT, unsigned ShiftOpc, bool MayTransformRotate,
|
| H A D | X86ISelLowering.cpp | 3365 EVT VT, unsigned ShiftOpc, bool MayTransformRotate, in preferedOpcodeForCmpEqPiecesOfOperand() argument
3368 return ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3387 if (ShiftOpc == ISD::SHL || ShiftOpc == ISD::SRL) { in preferedOpcodeForCmpEqPiecesOfOperand()
3397 return ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3400 if (ShiftOpc == ISD::SHL) { in preferedOpcodeForCmpEqPiecesOfOperand()
3405 : ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3410 return ShiftOrRotateAmt.uge(7) ? (unsigned)ISD::SRL : ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3416 return AndMask->getSignificantBits() > 33 ? (unsigned)ISD::SHL : ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3419 return ShiftOrRotateAmt.ult(7) ? (unsigned)ISD::SHL : ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3425 return ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 894 EVT VT, unsigned ShiftOpc, bool MayTransformRotate, in preferedOpcodeForCmpEqPiecesOfOperand() argument
897 return ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1675 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegImmOperand()
1715 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegRegOperand()
2113 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; in DecodeAddrMode2IdxInstruction()
2159 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 1010 unsigned ShiftOpc = Op.getOpcode(); in combineShiftToAVG() local
1022 switch (ShiftOpc) { in combineShiftToAVG()
9310 unsigned ShiftOpc = IsSigned ? ISD::SRA : ISD::SRL; in expandAVG() local
9326 return DAG.getNode(ShiftOpc, dl, VT, Sum, in expandAVG()
9357 DAG.getNode(ShiftOpc, dl, VT, Xor, DAG.getShiftAmountConstant(1, VT, dl)); in expandAVG()
|
| H A D | DAGCombiner.cpp | 12729 unsigned ShiftOpc = ShiftOrRotate.getOpcode(); in visitSETCC() local
12739 ShiftOpc == ISD::SHL ? (~*AndCMask).isMask() : AndCMask->isMask(); in visitSETCC()
12744 OpVT, ShiftOpc, ShiftCAmt->isPowerOf2(), *ShiftCAmt, AndCMask); in visitSETCC()
12746 if (CanTransform && NewShiftOpc != ShiftOpc) { in visitSETCC()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 3649 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri; in tryBitfieldInsertOpFromOr() local
3659 ShiftOpc, DL, VT, Src, CurDAG->getTargetConstant(LsrImm, DL, VT), in tryBitfieldInsertOpFromOr()
|