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Searched refs:ShiftAmt (Results 1 – 25 of 70) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DKnownBits.cpp288 auto ShiftByConst = [&](const KnownBits &LHS, unsigned ShiftAmt) { in shl() argument
291 Known.Zero = LHS.Zero.ushl_ov(ShiftAmt, ShiftedOutZero); in shl()
292 Known.Zero.setLowBits(ShiftAmt); in shl()
293 Known.One = LHS.One.ushl_ov(ShiftAmt, ShiftedOutOne); in shl()
297 if (NUW && ShiftAmt != 0) in shl()
353 for (unsigned ShiftAmt = MinShiftAmount; ShiftAmt <= MaxShiftAmount; in shl() local
354 ++ShiftAmt) { in shl()
356 if ((ShiftAmtZeroMask & ShiftAmt) != 0 || in shl()
357 (ShiftAmtOneMask | ShiftAmt) != ShiftAmt) in shl()
359 Known = Known.intersectWith(ShiftByConst(LHS, ShiftAmt)); in shl()
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H A DAPInt.cpp1026 void APInt::ashrSlowCase(unsigned ShiftAmt) { in ashrSlowCase() argument
1028 if (!ShiftAmt) in ashrSlowCase()
1035 unsigned WordShift = ShiftAmt / APINT_BITS_PER_WORD; in ashrSlowCase()
1036 unsigned BitShift = ShiftAmt % APINT_BITS_PER_WORD; in ashrSlowCase()
1075 void APInt::lshrSlowCase(unsigned ShiftAmt) { in lshrSlowCase() argument
1076 tcShiftRight(U.pVal, getNumWords(), ShiftAmt); in lshrSlowCase()
1087 void APInt::shlSlowCase(unsigned ShiftAmt) { in shlSlowCase() argument
1088 tcShiftLeft(U.pVal, getNumWords(), ShiftAmt); in shlSlowCase()
2236 unsigned ShiftAmt = (Radix == 16 ? 4 : (Radix == 8 ? 3 : 1)); in toString() local
2246 Tmp.lshrInPlace(ShiftAmt); in toString()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DDemandedBits.cpp130 uint64_t ShiftAmt = SA->urem(BitWidth); in determineLiveOperandBits() local
132 ShiftAmt = BitWidth - ShiftAmt; in determineLiveOperandBits()
135 AB = AOut.lshr(ShiftAmt); in determineLiveOperandBits()
137 AB = AOut.shl(BitWidth - ShiftAmt); in determineLiveOperandBits()
178 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1); in determineLiveOperandBits() local
179 AB = AOut.lshr(ShiftAmt); in determineLiveOperandBits()
185 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1); in determineLiveOperandBits()
187 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt); in determineLiveOperandBits()
195 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1); in determineLiveOperandBits() local
196 AB = AOut.shl(ShiftAmt); in determineLiveOperandBits()
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/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DAPInt.h765 APInt &operator<<=(unsigned ShiftAmt) {
766 assert(ShiftAmt <= BitWidth && "Invalid shift amount");
768 if (ShiftAmt == BitWidth)
771 U.VAL <<= ShiftAmt;
774 shlSlowCase(ShiftAmt);
783 APInt &operator<<=(const APInt &ShiftAmt);
807 APInt ashr(unsigned ShiftAmt) const { in ashr() argument
809 R.ashrInPlace(ShiftAmt); in ashr()
814 void ashrInPlace(unsigned ShiftAmt) { in ashrInPlace() argument
815 assert(ShiftAmt <= BitWidth && "Invalid shift amount"); in ashrInPlace()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp69 unsigned ShiftAmt = 0; in tryToreplicateChunks() local
72 for (; ShiftAmt < 64; ShiftAmt += 16) { in tryToreplicateChunks()
73 Imm16 = (UImm >> ShiftAmt) & 0xFFFF; in tryToreplicateChunks()
81 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); in tryToreplicateChunks()
89 for (ShiftAmt += 16; ShiftAmt < 64; ShiftAmt += 16) { in tryToreplicateChunks()
90 Imm16 = (UImm >> ShiftAmt) & 0xFFFF; in tryToreplicateChunks()
96 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); in tryToreplicateChunks()
H A DAArch64ConditionOptimizer.cpp175 unsigned ShiftAmt = AArch64_AM::getShiftValue(I.getOperand(3).getImm()); in findSuitableCompare() local
179 } else if (I.getOperand(2).getImm() << ShiftAmt >= 0xfff) { in findSuitableCompare()
H A DAArch64ISelDAGToDAG.cpp603 unsigned ShiftAmt; in SelectArithImmed() local
606 ShiftAmt = 0; in SelectArithImmed()
608 ShiftAmt = 12; in SelectArithImmed()
613 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt); in SelectArithImmed()
2856 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); in getUsefulBitsFromOrWithShiftedReg() local
2857 Mask <<= ShiftAmt; in getUsefulBitsFromOrWithShiftedReg()
2859 Mask.lshrInPlace(ShiftAmt); in getUsefulBitsFromOrWithShiftedReg()
2864 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); in getUsefulBitsFromOrWithShiftedReg() local
2865 Mask.lshrInPlace(ShiftAmt); in getUsefulBitsFromOrWithShiftedReg()
2867 Mask <<= ShiftAmt; in getUsefulBitsFromOrWithShiftedReg()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp658 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth - 1); in SimplifyDemandedUseBits() local
659 if (DemandedMask.countr_zero() >= ShiftAmt) { in SimplifyDemandedUseBits()
664 if (SignBits > ShiftAmt && SignBits - ShiftAmt >= NumHiDemandedBits) in SimplifyDemandedUseBits()
675 Constant *LeftShiftAmtC = ConstantInt::get(VTy, ShiftAmt); in SimplifyDemandedUseBits()
686 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt)); in SimplifyDemandedUseBits()
691 DemandedMaskIn.setHighBits(ShiftAmt+1); in SimplifyDemandedUseBits()
693 DemandedMaskIn.setHighBits(ShiftAmt); in SimplifyDemandedUseBits()
699 KnownBits::makeConstant(APInt(BitWidth, ShiftAmt)), in SimplifyDemandedUseBits()
721 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in SimplifyDemandedUseBits() local
740 if (DemandedMask.countl_zero() >= ShiftAmt) { in SimplifyDemandedUseBits()
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H A DInstCombineCasts.cpp1080 uint64_t ShiftAmt = Amt->getZExtValue(); in canEvaluateZExtd() local
1081 BitsToClear = ShiftAmt < BitsToClear ? BitsToClear - ShiftAmt : 0; in canEvaluateZExtd()
1338 unsigned ShiftAmt = KnownZeroMask.countr_zero(); in transformSExtICmp() local
1340 if (ShiftAmt) in transformSExtICmp()
1342 ConstantInt::get(In->getType(), ShiftAmt)); in transformSExtICmp()
1352 unsigned ShiftAmt = KnownZeroMask.countl_zero(); in transformSExtICmp() local
1354 if (ShiftAmt) in transformSExtICmp()
1356 ConstantInt::get(In->getType(), ShiftAmt)); in transformSExtICmp()
H A DInstCombineCompares.cpp2307 const APInt *ShiftAmt; in foldICmpShlConstant() local
2308 if (!match(Shl->getOperand(1), m_APInt(ShiftAmt))) in foldICmpShlConstant()
2314 if (ShiftAmt->uge(TypeBits)) in foldICmpShlConstant()
2326 APInt ShiftedC = C.ashr(*ShiftAmt); in foldICmpShlConstant()
2330 C.ashr(*ShiftAmt).shl(*ShiftAmt) == C) { in foldICmpShlConstant()
2331 APInt ShiftedC = C.ashr(*ShiftAmt); in foldICmpShlConstant()
2340 APInt ShiftedC = (C - 1).ashr(*ShiftAmt) + 1; in foldICmpShlConstant()
2351 APInt ShiftedC = C.lshr(*ShiftAmt); in foldICmpShlConstant()
2355 C.lshr(*ShiftAmt).shl(*ShiftAmt) == C) { in foldICmpShlConstant()
2356 APInt ShiftedC = C.lshr(*ShiftAmt); in foldICmpShlConstant()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DVNCoercion.cpp140 uint64_t ShiftAmt = DL.getTypeStoreSizeInBits(StoredValTy).getFixedValue() - in coerceAvailableValueToLoadType() local
143 StoredVal, ConstantInt::get(StoredVal->getType(), ShiftAmt)); in coerceAvailableValueToLoadType()
320 unsigned ShiftAmt; in getStoreValueForLoadHelper() local
322 ShiftAmt = Offset * 8; in getStoreValueForLoadHelper()
324 ShiftAmt = (StoreSize - LoadSize - Offset) * 8; in getStoreValueForLoadHelper()
325 if (ShiftAmt) in getStoreValueForLoadHelper()
327 ConstantInt::get(SrcVal->getType(), ShiftAmt)); in getStoreValueForLoadHelper()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp325 int64_t ShiftAmt; in matchCvtF32UByteN() local
326 IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt))); in matchCvtF32UByteN()
327 if (IsShr || mi_match(SrcReg, MRI, m_GShl(m_Reg(Src0), m_ICst(ShiftAmt)))) { in matchCvtF32UByteN()
332 ShiftOffset += ShiftAmt; in matchCvtF32UByteN()
334 ShiftOffset -= ShiftAmt; in matchCvtF32UByteN()
H A DAMDGPUISelDAGToDAG.cpp70 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) { in isExtractHiElt() local
71 if (ShiftAmt->getZExtValue() == 16) { in isExtractHiElt()
3422 ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); in SelectSWMMACIndex8() local
3423 if (ShiftSrc.getValueType().getSizeInBits() == 32 && ShiftAmt && in SelectSWMMACIndex8()
3424 ShiftAmt->getZExtValue() % 8 == 0) { in SelectSWMMACIndex8()
3425 Key = ShiftAmt->getZExtValue() / 8; in SelectSWMMACIndex8()
3441 ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); in SelectSWMMACIndex16() local
3442 if (ShiftSrc.getValueType().getSizeInBits() == 32 && ShiftAmt && in SelectSWMMACIndex16()
3443 ShiftAmt->getZExtValue() == 16) { in SelectSWMMACIndex16()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAtomicExpandPass.cpp687 Value *ShiftAmt = nullptr; member
710 PrintObj(PMV.ShiftAmt); in operator <<()
758 PMV.ShiftAmt = ConstantInt::get(PMV.ValueType, 0); in createMaskInstrs()
787 PMV.ShiftAmt = Builder.CreateShl(PtrLSB, 3); in createMaskInstrs()
790 PMV.ShiftAmt = Builder.CreateShl( in createMaskInstrs()
794 PMV.ShiftAmt = Builder.CreateTrunc(PMV.ShiftAmt, PMV.WordType, "ShiftAmt"); in createMaskInstrs()
796 ConstantInt::get(PMV.WordType, (1 << (ValueSize * 8)) - 1), PMV.ShiftAmt, in createMaskInstrs()
810 Value *Shift = Builder.CreateLShr(WideWord, PMV.ShiftAmt, "shifted"); in extractMaskedValue()
826 Builder.CreateShl(ZExt, PMV.ShiftAmt, "shifted", /*HasNUW*/ true); in insertMaskedValue()
915 Builder.CreateShl(Builder.CreateZExt(ValOp, PMV.WordType), PMV.ShiftAmt, in expandPartwordAtomicRMW()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1905 ISD::NodeType Opc, int64_t ShiftAmt) { in insertMultibyteShift() argument
1923 if (ShiftLeft && (ShiftAmt % 8) >= 6) { in insertMultibyteShift()
1928 size_t ShiftRegsOffset = ShiftAmt / 8; in insertMultibyteShift()
1943 if (ShiftAmt % 8 == 6) { in insertMultibyteShift()
1966 if (!ShiftLeft && (ShiftAmt % 8) >= 6) { in insertMultibyteShift()
1969 size_t ShiftRegsSize = Regs.size() - (ShiftAmt / 8); in insertMultibyteShift()
2000 if (ShiftAmt % 8 == 6) { in insertMultibyteShift()
2027 while (ShiftLeft && ShiftAmt >= 8) { in insertMultibyteShift()
2039 ShiftAmt -= 8; in insertMultibyteShift()
2044 if (!ShiftLeft && ShiftAmt >= 8) { in insertMultibyteShift()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp185 unsigned ShiftAmt, AddSubOpc; in matchAArch64MulConstCombine() local
198 ShiftAmt = SCVMinus1.logBase2(); in matchAArch64MulConstCombine()
201 ShiftAmt = CVPlus1.logBase2(); in matchAArch64MulConstCombine()
211 ShiftAmt = CVNegPlus1.logBase2(); in matchAArch64MulConstCombine()
215 ShiftAmt = CVNegMinus1.logBase2(); in matchAArch64MulConstCombine()
226 auto Shift = B.buildConstant(LLT::scalar(64), ShiftAmt); in matchAArch64MulConstCombine()
H A DAArch64PostLegalizerLowering.cpp846 uint64_t ShiftAmt = MaybeShiftAmt->Value.getZExtValue(); in getCmpOperandFoldingProfit() local
854 return (ShiftAmt <= 4) ? 2 : 1; in getCmpOperandFoldingProfit()
860 if ((ShiftSize == 32 && ShiftAmt <= 31) || in getCmpOperandFoldingProfit()
861 (ShiftSize == 64 && ShiftAmt <= 63)) in getCmpOperandFoldingProfit()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp469 unsigned &ShiftAmt, unsigned &AddOpc) { in generateTwoRegInstSeq() argument
485 ShiftAmt = TzHi - TzLo; in generateTwoRegInstSeq()
488 if (Tmp == ((uint64_t)LoVal << ShiftAmt)) in generateTwoRegInstSeq()
493 ShiftAmt = 32; in generateTwoRegInstSeq()
H A DRISCVMatInt.h62 unsigned &ShiftAmt, unsigned &AddOpc);
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2121 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in foldMaskedShiftToScaledMask() local
2122 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3) in foldMaskedShiftToScaledMask()
2133 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT); in foldMaskedShiftToScaledMask()
2148 AM.Scale = 1 << ShiftAmt; in foldMaskedShiftToScaledMask()
2194 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in foldMaskAndShiftToScale() local
2206 unsigned ScaleDown = (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt; in foldMaskAndShiftToScale()
2245 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8); in foldMaskAndShiftToScale()
2292 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in foldMaskedShiftToBEXTR() local
2305 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8); in foldMaskedShiftToBEXTR()
2367 uint64_t ShiftAmt = N.getConstantOperandVal(1); in matchIndexRecursively() local
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLoadStoreOpt.cpp664 int64_t ShiftAmt; in getTruncStoreByteOffset() local
666 m_any_of(m_GLShr(m_Reg(FoundSrcVal), m_ICst(ShiftAmt)), in getTruncStoreByteOffset()
667 m_GAShr(m_Reg(FoundSrcVal), m_ICst(ShiftAmt))))) { in getTruncStoreByteOffset()
677 if (ShiftAmt % NarrowBits != 0) in getTruncStoreByteOffset()
679 const unsigned Offset = ShiftAmt / NarrowBits; in getTruncStoreByteOffset()
H A DLegalizerHelper.cpp280 auto ShiftAmt = in buildLCMMergePieces() local
282 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); in buildLCMMergePieces()
1879 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); in widenScalarMergeValues() local
1880 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); in widenScalarMergeValues()
2009 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); in widenScalarUnmergeValues() local
2010 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); in widenScalarUnmergeValues()
2537 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); in widenScalar() local
2538 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt); in widenScalar()
3585 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); in lowerLoad() local
3586 auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt); in lowerLoad()
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H A DCombinerHelper.cpp2064 int64_t ShiftAmt = MaybeShiftAmtVal->getSExtValue(); in matchCombineShlOfExtend() local
2066 MatchData.Imm = ShiftAmt; in matchCombineShlOfExtend()
2070 return MinLeadingZeros >= ShiftAmt && ShiftAmt < SrcTySize; in matchCombineShlOfExtend()
2079 auto ShiftAmt = Builder.buildConstant(ExtSrcTy, ShiftAmtVal); in applyCombineShlOfExtend() local
2081 Builder.buildShl(ExtSrcTy, ExtSrcReg, ShiftAmt, MI.getFlags()); in applyCombineShlOfExtend()
2183 unsigned ShiftAmt = Dst0Ty.getSizeInBits(); in matchCombineUnmergeConstant() local
2186 Csts.emplace_back(Val.trunc(ShiftAmt)); in matchCombineUnmergeConstant()
2187 Val = Val.lshr(ShiftAmt); in matchCombineUnmergeConstant()
2400 unsigned ShiftAmt; in tryCombineShiftToUnmerge() local
2401 if (matchCombineShiftToUnmerge(MI, TargetShiftAmount, ShiftAmt)) { in tryCombineShiftToUnmerge()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp221 unsigned ShiftAmt, AddOpc; in selectImm() local
223 RISCVMatInt::generateTwoRegInstSeq(Imm, Subtarget, ShiftAmt, AddOpc); in selectImm()
229 CurDAG->getTargetConstant(ShiftAmt, DL, VT)), in selectImm()
2528 uint64_t ShiftAmt = 0; in SelectAddrRegRegScale() local
2535 ShiftAmt = N.getConstantOperandVal(1); in SelectAddrRegRegScale()
2539 Shift = CurDAG->getTargetConstant(ShiftAmt, SDLoc(N), VT); in SelectAddrRegRegScale()
2540 return ShiftAmt != 0; in SelectAddrRegRegScale()
2889 auto UnwrapShlSra = [](SDValue N, unsigned ShiftAmt) { in selectSExtBits() argument
2895 N.getConstantOperandVal(1) == ShiftAmt && in selectSExtBits()
2896 N0.getConstantOperandVal(1) == ShiftAmt) in selectSExtBits()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1825 unsigned ShiftAmt; in emitIntSExt32r1() local
1830 ShiftAmt = 24; in emitIntSExt32r1()
1833 ShiftAmt = 16; in emitIntSExt32r1()
1837 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); in emitIntSExt32r1()
1838 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); in emitIntSExt32r1()

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