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Searched refs:ShiftAmt (Results 1 – 25 of 77) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DKnownBits.cpp288 auto ShiftByConst = [&](const KnownBits &LHS, unsigned ShiftAmt) { in shl() argument
291 Known.Zero = LHS.Zero.ushl_ov(ShiftAmt, ShiftedOutZero); in shl()
292 Known.Zero.setLowBits(ShiftAmt); in shl()
293 Known.One = LHS.One.ushl_ov(ShiftAmt, ShiftedOutOne); in shl()
297 if (NUW && ShiftAmt != 0) in shl()
353 for (unsigned ShiftAmt = MinShiftAmount; ShiftAmt <= MaxShiftAmount; in shl() local
354 ++ShiftAmt) { in shl()
356 if ((ShiftAmtZeroMask & ShiftAmt) != 0 || in shl()
357 (ShiftAmtOneMask | ShiftAmt) != ShiftAmt) in shl()
359 Known = Known.intersectWith(ShiftByConst(LHS, ShiftAmt)); in shl()
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H A DAPInt.cpp1057 void APInt::ashrSlowCase(unsigned ShiftAmt) { in ashrSlowCase() argument
1059 if (!ShiftAmt) in ashrSlowCase()
1066 unsigned WordShift = ShiftAmt / APINT_BITS_PER_WORD; in ashrSlowCase()
1067 unsigned BitShift = ShiftAmt % APINT_BITS_PER_WORD; in ashrSlowCase()
1105 void APInt::lshrSlowCase(unsigned ShiftAmt) { in lshrSlowCase() argument
1106 tcShiftRight(U.pVal, getNumWords(), ShiftAmt); in lshrSlowCase()
1117 void APInt::shlSlowCase(unsigned ShiftAmt) { in shlSlowCase() argument
1118 tcShiftLeft(U.pVal, getNumWords(), ShiftAmt); in shlSlowCase()
2266 unsigned ShiftAmt = (Radix == 16 ? 4 : (Radix == 8 ? 3 : 1)); in toString() local
2276 Tmp.lshrInPlace(ShiftAmt); in toString()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DDemandedBits.cpp128 uint64_t ShiftAmt = SA->urem(BitWidth); in determineLiveOperandBits() local
130 ShiftAmt = BitWidth - ShiftAmt; in determineLiveOperandBits()
133 AB = AOut.lshr(ShiftAmt); in determineLiveOperandBits()
135 AB = AOut.shl(BitWidth - ShiftAmt); in determineLiveOperandBits()
176 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1); in determineLiveOperandBits() local
177 AB = AOut.lshr(ShiftAmt); in determineLiveOperandBits()
183 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1); in determineLiveOperandBits()
185 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt); in determineLiveOperandBits()
193 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1); in determineLiveOperandBits() local
194 AB = AOut.shl(ShiftAmt); in determineLiveOperandBits()
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/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DAPInt.h785 APInt &operator<<=(unsigned ShiftAmt) {
786 assert(ShiftAmt <= BitWidth && "Invalid shift amount");
788 if (ShiftAmt == BitWidth)
791 U.VAL <<= ShiftAmt;
794 shlSlowCase(ShiftAmt);
803 LLVM_ABI APInt &operator<<=(const APInt &ShiftAmt);
827 APInt ashr(unsigned ShiftAmt) const { in ashr() argument
829 R.ashrInPlace(ShiftAmt); in ashr()
834 void ashrInPlace(unsigned ShiftAmt) { in ashrInPlace() argument
835 assert(ShiftAmt <= BitWidth && "Invalid shift amount"); in ashrInPlace()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp69 unsigned ShiftAmt = 0; in tryToreplicateChunks() local
72 for (; ShiftAmt < 64; ShiftAmt += 16) { in tryToreplicateChunks()
73 Imm16 = (UImm >> ShiftAmt) & 0xFFFF; in tryToreplicateChunks()
81 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); in tryToreplicateChunks()
89 for (ShiftAmt += 16; ShiftAmt < 64; ShiftAmt += 16) { in tryToreplicateChunks()
90 Imm16 = (UImm >> ShiftAmt) & 0xFFFF; in tryToreplicateChunks()
96 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); in tryToreplicateChunks()
H A DAArch64ConditionOptimizer.cpp173 unsigned ShiftAmt = AArch64_AM::getShiftValue(I.getOperand(3).getImm()); in findSuitableCompare() local
177 } else if (I.getOperand(2).getImm() << ShiftAmt >= 0xfff) { in findSuitableCompare()
H A DAArch64ISelDAGToDAG.cpp603 unsigned ShiftAmt; in SelectArithImmed() local
606 ShiftAmt = 0; in SelectArithImmed()
608 ShiftAmt = 12; in SelectArithImmed()
613 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt); in SelectArithImmed()
2958 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); in getUsefulBitsFromOrWithShiftedReg() local
2959 Mask <<= ShiftAmt; in getUsefulBitsFromOrWithShiftedReg()
2961 Mask.lshrInPlace(ShiftAmt); in getUsefulBitsFromOrWithShiftedReg()
2966 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); in getUsefulBitsFromOrWithShiftedReg() local
2967 Mask.lshrInPlace(ShiftAmt); in getUsefulBitsFromOrWithShiftedReg()
2969 Mask <<= ShiftAmt; in getUsefulBitsFromOrWithShiftedReg()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp673 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth - 1); in SimplifyDemandedUseBits() local
674 if (DemandedMask.countr_zero() >= ShiftAmt) { in SimplifyDemandedUseBits()
679 if (SignBits > ShiftAmt && SignBits - ShiftAmt >= NumHiDemandedBits) in SimplifyDemandedUseBits()
690 Constant *LeftShiftAmtC = ConstantInt::get(VTy, ShiftAmt); in SimplifyDemandedUseBits()
701 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt)); in SimplifyDemandedUseBits()
706 DemandedMaskIn.setHighBits(ShiftAmt+1); in SimplifyDemandedUseBits()
708 DemandedMaskIn.setHighBits(ShiftAmt); in SimplifyDemandedUseBits()
714 KnownBits::makeConstant(APInt(BitWidth, ShiftAmt)), in SimplifyDemandedUseBits()
736 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in SimplifyDemandedUseBits() local
755 if (DemandedMask.countl_zero() >= ShiftAmt) { in SimplifyDemandedUseBits()
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H A DInstCombineCasts.cpp1134 uint64_t ShiftAmt = Amt->getZExtValue(); in canEvaluateZExtd() local
1135 BitsToClear = ShiftAmt < BitsToClear ? BitsToClear - ShiftAmt : 0; in canEvaluateZExtd()
1389 unsigned ShiftAmt = KnownZeroMask.countr_zero(); in transformSExtICmp() local
1391 if (ShiftAmt) in transformSExtICmp()
1393 ConstantInt::get(In->getType(), ShiftAmt)); in transformSExtICmp()
1403 unsigned ShiftAmt = KnownZeroMask.countl_zero(); in transformSExtICmp() local
1405 if (ShiftAmt) in transformSExtICmp()
1407 ConstantInt::get(In->getType(), ShiftAmt)); in transformSExtICmp()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DVNCoercion.cpp163 uint64_t ShiftAmt = DL.getTypeStoreSizeInBits(StoredValTy).getFixedValue() - in coerceAvailableValueToLoadType() local
166 StoredVal, ConstantInt::get(StoredVal->getType(), ShiftAmt)); in coerceAvailableValueToLoadType()
360 unsigned ShiftAmt; in getStoreValueForLoadHelper() local
362 ShiftAmt = Offset * 8; in getStoreValueForLoadHelper()
364 ShiftAmt = (StoreSize - LoadSize - Offset) * 8; in getStoreValueForLoadHelper()
365 if (ShiftAmt) in getStoreValueForLoadHelper()
367 ConstantInt::get(SrcVal->getType(), ShiftAmt)); in getStoreValueForLoadHelper()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAtomicExpandPass.cpp762 Value *ShiftAmt = nullptr; member
785 PrintObj(PMV.ShiftAmt); in operator <<()
833 PMV.ShiftAmt = ConstantInt::get(PMV.ValueType, 0); in createMaskInstrs()
862 PMV.ShiftAmt = Builder.CreateShl(PtrLSB, 3); in createMaskInstrs()
865 PMV.ShiftAmt = Builder.CreateShl( in createMaskInstrs()
869 PMV.ShiftAmt = Builder.CreateTrunc(PMV.ShiftAmt, PMV.WordType, "ShiftAmt"); in createMaskInstrs()
871 ConstantInt::get(PMV.WordType, (1 << (ValueSize * 8)) - 1), PMV.ShiftAmt, in createMaskInstrs()
885 Value *Shift = Builder.CreateLShr(WideWord, PMV.ShiftAmt, "shifted"); in extractMaskedValue()
901 Builder.CreateShl(ZExt, PMV.ShiftAmt, "shifted", /*HasNUW*/ true); in insertMaskedValue()
994 Builder.CreateShl(Builder.CreateZExt(ValOp, PMV.WordType), PMV.ShiftAmt, in expandPartwordAtomicRMW()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp325 int64_t ShiftAmt; in matchCvtF32UByteN() local
326 IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt))); in matchCvtF32UByteN()
327 if (IsShr || mi_match(SrcReg, MRI, m_GShl(m_Reg(Src0), m_ICst(ShiftAmt)))) { in matchCvtF32UByteN()
332 ShiftOffset += ShiftAmt; in matchCvtF32UByteN()
334 ShiftOffset -= ShiftAmt; in matchCvtF32UByteN()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1859 ISD::NodeType Opc, int64_t ShiftAmt) { in insertMultibyteShift() argument
1877 if (ShiftLeft && (ShiftAmt % 8) >= 6) { in insertMultibyteShift()
1882 size_t ShiftRegsOffset = ShiftAmt / 8; in insertMultibyteShift()
1897 if (ShiftAmt % 8 == 6) { in insertMultibyteShift()
1920 if (!ShiftLeft && (ShiftAmt % 8) >= 6) { in insertMultibyteShift()
1923 size_t ShiftRegsSize = Regs.size() - (ShiftAmt / 8); in insertMultibyteShift()
1954 if (ShiftAmt % 8 == 6) { in insertMultibyteShift()
1981 while (ShiftLeft && ShiftAmt >= 8) { in insertMultibyteShift()
1993 ShiftAmt -= 8; in insertMultibyteShift()
1998 if (!ShiftLeft && ShiftAmt >= 8) { in insertMultibyteShift()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp506 unsigned &ShiftAmt, unsigned &AddOpc) { in generateTwoRegInstSeq() argument
522 ShiftAmt = TzHi - TzLo; in generateTwoRegInstSeq()
525 if (Tmp == ((uint64_t)LoVal << ShiftAmt)) in generateTwoRegInstSeq()
530 ShiftAmt = 32; in generateTwoRegInstSeq()
H A DRISCVMatInt.h62 unsigned &ShiftAmt, unsigned &AddOpc);
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2179 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in foldMaskedShiftToScaledMask() local
2180 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3) in foldMaskedShiftToScaledMask()
2191 SDValue NewMask = DAG.getSignedConstant(Mask >> ShiftAmt, DL, VT); in foldMaskedShiftToScaledMask()
2206 AM.Scale = 1 << ShiftAmt; in foldMaskedShiftToScaledMask()
2252 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in foldMaskAndShiftToScale() local
2264 unsigned ScaleDown = (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt; in foldMaskAndShiftToScale()
2303 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8); in foldMaskAndShiftToScale()
2350 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in foldMaskedShiftToBEXTR() local
2363 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8); in foldMaskedShiftToBEXTR()
2425 uint64_t ShiftAmt = N.getConstantOperandVal(1); in matchIndexRecursively() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp185 unsigned ShiftAmt, AddSubOpc; in matchAArch64MulConstCombine() local
198 ShiftAmt = SCVMinus1.logBase2(); in matchAArch64MulConstCombine()
201 ShiftAmt = CVPlus1.logBase2(); in matchAArch64MulConstCombine()
211 ShiftAmt = CVNegPlus1.logBase2(); in matchAArch64MulConstCombine()
215 ShiftAmt = CVNegMinus1.logBase2(); in matchAArch64MulConstCombine()
226 auto Shift = B.buildConstant(LLT::scalar(64), ShiftAmt); in matchAArch64MulConstCombine()
H A DAArch64PostLegalizerLowering.cpp862 uint64_t ShiftAmt = MaybeShiftAmt->Value.getZExtValue(); in getCmpOperandFoldingProfit() local
870 return (ShiftAmt <= 4) ? 2 : 1; in getCmpOperandFoldingProfit()
876 if ((ShiftSize == 32 && ShiftAmt <= 31) || in getCmpOperandFoldingProfit()
877 (ShiftSize == 64 && ShiftAmt <= 63)) in getCmpOperandFoldingProfit()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLoadStoreOpt.cpp659 int64_t ShiftAmt; in getTruncStoreByteOffset() local
661 m_any_of(m_GLShr(m_Reg(FoundSrcVal), m_ICst(ShiftAmt)), in getTruncStoreByteOffset()
662 m_GAShr(m_Reg(FoundSrcVal), m_ICst(ShiftAmt))))) { in getTruncStoreByteOffset()
672 if (ShiftAmt % NarrowBits != 0) in getTruncStoreByteOffset()
674 const unsigned Offset = ShiftAmt / NarrowBits; in getTruncStoreByteOffset()
H A DLegalizerHelper.cpp280 auto ShiftAmt = in buildLCMMergePieces() local
282 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); in buildLCMMergePieces()
2178 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); in widenScalarMergeValues() local
2179 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); in widenScalarMergeValues()
2307 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); in widenScalarUnmergeValues() local
2308 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); in widenScalarUnmergeValues()
2836 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); in widenScalar() local
2837 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt); in widenScalar()
4177 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); in lowerLoad() local
4178 auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt); in lowerLoad()
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H A DCombinerHelper.cpp2162 int64_t ShiftAmt = MaybeShiftAmtVal->getSExtValue(); in matchCombineShlOfExtend() local
2164 MatchData.Imm = ShiftAmt; in matchCombineShlOfExtend()
2168 return MinLeadingZeros >= ShiftAmt && ShiftAmt < SrcTySize; in matchCombineShlOfExtend()
2177 auto ShiftAmt = Builder.buildConstant(ExtSrcTy, ShiftAmtVal); in applyCombineShlOfExtend() local
2179 Builder.buildShl(ExtSrcTy, ExtSrcReg, ShiftAmt, MI.getFlags()); in applyCombineShlOfExtend()
2281 unsigned ShiftAmt = Dst0Ty.getSizeInBits(); in matchCombineUnmergeConstant() local
2284 Csts.emplace_back(Val.trunc(ShiftAmt)); in matchCombineUnmergeConstant()
2285 Val = Val.lshr(ShiftAmt); in matchCombineUnmergeConstant()
2501 unsigned ShiftAmt; in tryCombineShiftToUnmerge() local
2502 if (matchCombineShiftToUnmerge(MI, TargetShiftAmount, ShiftAmt)) { in tryCombineShiftToUnmerge()
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/freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/
H A DDXILIntrinsicExpansion.cpp712 Constant *ShiftAmt = Builder.getInt64(32); in expandBufferStoreIntrinsic() local
714 ShiftAmt = in expandBufferStoreIntrinsic()
715 ConstantVector::getSplat(ElementCount::getFixed(VecLen), ShiftAmt); in expandBufferStoreIntrinsic()
719 Value *ShiftedVal = Builder.CreateLShr(InputVal, ShiftAmt); in expandBufferStoreIntrinsic()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DPPC.cpp717 Constant *ShiftAmt = ConstantInt::get(Int64Ty, 32); in EmitPPCBuiltinExpr() local
719 Builder.CreateTrunc(Builder.CreateLShr(Op0, ShiftAmt), Int32Ty); in EmitPPCBuiltinExpr()
721 Builder.CreateTrunc(Builder.CreateLShr(Op1, ShiftAmt), Int32Ty); in EmitPPCBuiltinExpr()
726 Value *ResHi = Builder.CreateShl(ResHiShift, ShiftAmt); in EmitPPCBuiltinExpr()
832 Value *ShiftAmt = Builder.CreateIntCast(Op1, Ty, false); in EmitPPCBuiltinExpr() local
834 Value *Rotate = Builder.CreateCall(F, {Op0, Op0, ShiftAmt}); in EmitPPCBuiltinExpr()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp1766 uint64_t ShiftAmt = ShiftCnst->getZExtValue(); in tryBFE() local
1789 NumBits = llvm::countr_one(MaskVal) - ShiftAmt; in tryBFE()
1796 NumBits = NumZeros + NumOnes - ShiftAmt; in tryBFE()
1802 if (ShiftAmt < NumZeros) { in tryBFE()
1809 Start = CurDAG->getTargetConstant(ShiftAmt, DL, MVT::i32); in tryBFE()
1817 IsSigned = (ShiftAmt + NumBits) == Val.getValueSizeInBits(); in tryBFE()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp224 unsigned ShiftAmt, AddOpc; in selectImm() local
226 RISCVMatInt::generateTwoRegInstSeq(Imm, Subtarget, ShiftAmt, AddOpc); in selectImm()
232 CurDAG->getTargetConstant(ShiftAmt, DL, VT)), in selectImm()
3042 uint64_t ShiftAmt = 0; in SelectAddrRegRegScale() local
3049 ShiftAmt = N.getConstantOperandVal(1); in SelectAddrRegRegScale()
3053 Shift = CurDAG->getTargetConstant(ShiftAmt, SDLoc(N), VT); in SelectAddrRegRegScale()
3054 return ShiftAmt != 0; in SelectAddrRegRegScale()
3261 auto UnwrapShlSra = [](SDValue N, unsigned ShiftAmt) { in selectSExtBits() argument
3267 N.getConstantOperandVal(1) == ShiftAmt && in selectSExtBits()
3268 N0.getConstantOperandVal(1) == ShiftAmt) in selectSExtBits()

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