| /freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/ |
| H A D | Scheduler.cpp | 22 void Scheduler::initializeStrategy(std::unique_ptr<SchedulerStrategy> S) { in initializeStrategy() 32 void Scheduler::dump() const { in dump() 40 Scheduler::Status Scheduler::isAvailable(const InstRef &IR) { in isAvailable() 47 return Scheduler::SC_BUFFERS_FULL; in isAvailable() 49 return Scheduler::SC_DISPATCH_GROUP_STALL; in isAvailable() 60 return Scheduler::SC_LOAD_QUEUE_FULL; in isAvailable() 62 return Scheduler::SC_STORE_QUEUE_FULL; in isAvailable() 64 return Scheduler::SC_AVAILABLE; in isAvailable() 70 void Scheduler::issueInstructionImpl( in issueInstructionImpl() 100 void Scheduler::issueInstruction( in issueInstruction() [all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/ |
| H A D | Scheduler.h | 163 class Scheduler { 215 Scheduler(const Scheduler &) = delete; 216 Scheduler &operator=(const Scheduler &) = delete; 219 Scheduler(AAResults &AA, Context &Ctx) : DAG(AA, Ctx), Ctx(Ctx) { in Scheduler() function 225 ~Scheduler() { in ~Scheduler() 258 static DependencyGraph &getDAG(Scheduler &Sched) { return Sched.DAG; } in getDAG() 259 using BndlSchedState = Scheduler::BndlSchedState; 260 static BndlSchedState getBndlSchedState(const Scheduler &Sched, in getBndlSchedState()
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| H A D | Legality.h | 319 Scheduler Sched;
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/SandboxVectorizer/ |
| H A D | Scheduler.cpp | 69 void Scheduler::scheduleAndUpdateReadyList(SchedBundle &Bndl) { in scheduleAndUpdateReadyList() 89 void Scheduler::notifyCreateInstr(Instruction *I) { in notifyCreateInstr() 114 SchedBundle *Scheduler::createBundle(ArrayRef<Instruction *> Instrs) { in createBundle() 125 void Scheduler::eraseBundle(SchedBundle *SB) { Bndls.erase(SB); } in eraseBundle() 127 bool Scheduler::tryScheduleUntil(ArrayRef<Instruction *> Instrs) { in tryScheduleUntil() 205 Scheduler::BndlSchedState 206 Scheduler::getBndlSchedState(ArrayRef<Instruction *> Instrs) const { in getBndlSchedState() 240 void Scheduler::trimSchedule(ArrayRef<Instruction *> Instrs) { in trimSchedule() 290 bool Scheduler::trySchedule(ArrayRef<Instruction *> Instrs) { in trySchedule() 347 void Scheduler::dump(raw_ostream &OS) const { in dump() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PostRASchedulerList.cpp | 298 SchedulePostRATDList Scheduler(MF, *MLI, AA, RegClassInfo, AntiDepMode, in run() local 315 Scheduler.startBlock(&MBB); in run() 328 Scheduler.enterRegion(&MBB, I, Current, CurrentCount - Count); in run() 329 Scheduler.setEndIndex(CurrentCount); in run() 330 Scheduler.schedule(); in run() 331 Scheduler.exitRegion(); in run() 332 Scheduler.EmitSchedule(); in run() 335 Scheduler.Observe(MI, CurrentCount); in run() 344 Scheduler.enterRegion(&MBB, MBB.begin(), Current, CurrentCount); in run() 345 Scheduler.setEndIndex(CurrentCount); in run() [all …]
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| H A D | MachineScheduler.cpp | 323 void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags); 546 ScheduleDAGInstrs *Scheduler = TM->createMachineScheduler(this); in createMachineScheduler() local 547 if (Scheduler) in createMachineScheduler() 548 return Scheduler; in createMachineScheduler() 575 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler()); in run() local 576 scheduleRegions(*Scheduler, false); in run() 594 ScheduleDAGInstrs *Scheduler = TM->createPostMachineScheduler(this); in createPostMachineScheduler() local 595 if (Scheduler) in createPostMachineScheduler() 596 return Scheduler; in createPostMachineScheduler() 620 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler()); in run() local [all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/ |
| H A D | Scheduler.h | 71 class Scheduler : public HardwareUnit { 158 Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu) in Scheduler() function 159 : Scheduler(Model, Lsu, nullptr) {} in Scheduler() 161 Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu, in Scheduler() function 163 : Scheduler(std::make_unique<ResourceManager>(Model), Lsu, in Scheduler() 166 Scheduler(std::unique_ptr<ResourceManager> RM, LSUnitBase &Lsu, in Scheduler() function
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| /freebsd/contrib/llvm-project/llvm/lib/MCA/Stages/ |
| H A D | ExecuteStage.cpp | 26 HWStallEvent::GenericEventType toHWStallEventType(Scheduler::Status Status) { in toHWStallEventType() 28 case Scheduler::SC_LOAD_QUEUE_FULL: in toHWStallEventType() 30 case Scheduler::SC_STORE_QUEUE_FULL: in toHWStallEventType() 32 case Scheduler::SC_BUFFERS_FULL: in toHWStallEventType() 34 case Scheduler::SC_DISPATCH_GROUP_STALL: in toHWStallEventType() 36 case Scheduler::SC_AVAILABLE: in toHWStallEventType() 44 if (Scheduler::Status S = HWS.isAvailable(IR)) { in isAvailable()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/Stages/ |
| H A D | ExecuteStage.h | 29 Scheduler &HWS; 50 ExecuteStage(Scheduler &S) : ExecuteStage(S, false) {} in ExecuteStage() 51 ExecuteStage(Scheduler &S, bool ShouldPerformBottleneckAnalysis) in ExecuteStage()
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| /freebsd/crypto/heimdal/appl/telnet/telnet/ |
| H A D | authenc.c | 68 if (Scheduler(0) == -1) in telnet_spin()
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| H A D | externs.h | 184 int Scheduler(int);
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| H A D | telnet.c | 1980 Scheduler(int block) /* should we block in the select ? */ in Scheduler() function 2146 while ((schedValue = Scheduler(0)) != 0) { in my_telnet() 2153 if (Scheduler(1) == -1) { in my_telnet()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 1717 SIScheduleBlockScheduler Scheduler(DAG, ScheduleVariant, Blocks); in scheduleVariant() local 1721 ScheduledBlocks = Scheduler.getBlocks(); in scheduleVariant() 1730 Res.MaxSGPRUsage = Scheduler.getSGPRUsage(); in scheduleVariant() 1731 Res.MaxVGPRUsage = Scheduler.getVGPRUsage(); in scheduleVariant() 1908 SIScheduler Scheduler(this); in schedule() local 1909 Best = Scheduler.scheduleVariant(SISchedulerBlockCreatorVariant::LatenciesAlone, in schedule() 1928 Temp = Scheduler.scheduleVariant(v.first, v.second); in schedule() 1949 Temp = Scheduler.scheduleVariant(v.first, v.second); in schedule()
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| /freebsd/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | Context.cpp | 44 auto HWS = std::make_unique<Scheduler>(SM, *LSU); in createDefaultPipeline()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiSchedule.td | 44 // Enable Post RegAlloc Scheduler pass. [default = 0]
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | da8xx-usb.txt | 34 CPPI DMA Scheduler, Queue Manager
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| H A D | am33xx-usb.txt | 58 CPPI DMA Controller, USB CPPI DMA Scheduler, USB Queue Manager
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSchedule.td | 9 // Scheduler resources
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| /freebsd/contrib/file/magic/Magdir/ |
| H A D | wordprocessors | 298 # Corel Scheduler 300 >>9 byte 2 Corel Scheduler help file 301 >>9 byte 10 Corel Scheduler in file 302 >>9 byte 11 Corel Scheduler out file 304 >>>9 byte x Corel Scheduler: Unknown filetype %d
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64Schedule.td | 18 // AArch64 Scheduler Definitions
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| /freebsd/sys/contrib/device-tree/Bindings/soc/ti/ |
| H A D | keystone-navigator-dma.txt | 48 - Tx DMA channel Scheduler configuration register region (txsched).
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| /freebsd/contrib/telnet/telnet/ |
| H A D | telnet.c | 2058 Scheduler(int block) in Scheduler() function 2154 while ((schedValue = Scheduler(0)) != 0) { in telnet() 2161 if (Scheduler(1) == -1) { in telnet()
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| /freebsd/sys/contrib/openzfs/cmd/zpool_influxdb/ |
| H A D | README.md | 120 [ZFS documentation for ZIO Scheduler] 121 (https://openzfs.github.io/openzfs-docs/Performance%20and%20Tuning/ZIO%20Scheduler.html)
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| /freebsd/contrib/wpa/wpa_supplicant/ |
| H A D | README-Windows.txt | 151 description: Atheros Wireless Network Adapter (Microsoft's Packet Scheduler) 154 description: Intel 8255x-based Integrated Fast Ethernet (Microsoft's Packet Scheduler)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ScheduleBdVer2.td | 29 let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass. 95 // There is one Integer Scheduler per core. 100 // Unified Integer, Memory Scheduler has 40 entries. 117 // Unified FP Scheduler has 64 entries,
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