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Searched refs:Sched (Results 1 – 25 of 110) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepTimingClasses.h20 case Hexagon::Sched::tc_112d30d6: in is_TC1()
21 case Hexagon::Sched::tc_151bf368: in is_TC1()
22 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
23 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
24 case Hexagon::Sched::tc_23708a21: in is_TC1()
25 case Hexagon::Sched::tc_24f426ab: in is_TC1()
26 case Hexagon::Sched::tc_2f573607: in is_TC1()
27 case Hexagon::Sched::tc_388f9897: in is_TC1()
28 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
29 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp66 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
95 case PPC::Sched::IIC_IntDivW: in mustComeFirst()
96 case PPC::Sched::IIC_IntDivD: in mustComeFirst()
97 case PPC::Sched::IIC_LdStLoadUpd: in mustComeFirst()
98 case PPC::Sched::IIC_LdStLDU: in mustComeFirst()
99 case PPC::Sched::IIC_LdStLFDU: in mustComeFirst()
100 case PPC::Sched::IIC_LdStLFDUX: in mustComeFirst()
101 case PPC::Sched::IIC_LdStLHA: in mustComeFirst()
102 case PPC::Sched::IIC_LdStLHAU: in mustComeFirst()
103 case PPC::Sched::IIC_LdStLWA: in mustComeFirst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrExtension.td16 "{cbtw|cbw}", []>, OpSize16, Sched<[WriteALU]>;
19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
22 "{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
28 "{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
34 "{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
41 TB, OpSize16, Sched<[WriteALU]>;
45 TB, OpSize16, Sched<[WriteLoad]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteLoad]>;
[all …]
H A DX86InstrControl.td112 OpSize16, Sched<[WriteJump]>;
115 OpSize16, Sched<[WriteJumpLd]>;
119 OpSize32, Sched<[WriteJump]>;
122 OpSize32, Sched<[WriteJumpLd]>;
126 Sched<[WriteJump]>;
129 Sched<[WriteJumpLd]>;
135 "rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJump]>;
138 "rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJumpLd]>;
146 OpSize16, Sched<[WriteJump]>, NOTRACK;
150 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>,
[all …]
H A DX86InstrTBM.td22 X86FoldableSchedWrite Sched> {
27 XOP, XOPA, Sched<[Sched]>;
33 XOP, XOPA, Sched<[Sched.Folded]>;
45 X86MemOperand x86memop, X86FoldableSchedWrite Sched> {
49 XOP, VVVV, XOP9, Sched<[Sched]>;
53 XOP, VVVV, XOP9, Sched<[Sched
[all...]
H A DX86InstrXOP.td16 [(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[SchedWriteVecALU.XMM]>;
20 Sched<[SchedWriteVecALU.XMM.Folded, SchedWriteVecALU.XMM.ReadAfterFold]>;
47 [(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[sched]>;
51 Sched<[sched.Folded, sched.ReadAfterFold]>;
58 [(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[sched]>;
62 Sched<[sched.Folded, sched.ReadAfterFold]>;
69 [(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L, Sched<[sched]>;
73 Sched<[sched.Folded, sched.ReadAfterFold]>;
101 XOP, Sched<[sched]>;
108 XOP, VVVV, REX_W, Sched<[sche
[all...]
H A DX86InstrMMX.td41 Sched<[sched]> {
48 Sched<[sched.Folded, sched.ReadAfterFold]>;
59 Sched<[sched]>;
64 Sched<[sched.Folded, sched.ReadAfterFold]>;
69 Sched<[schedImm]>;
79 Sched<[sched]>;
84 Sched<[sched.Folded]>;
97 Sched<[sched]>;
103 Sched<[sched.Folded, sched.ReadAfterFold]>;
114 Sched<[sched]>;
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H A DX86InstrSSE.td31 Sched<[sched]>;
38 Sched<[sched.Folded, sched.ReadAfterFold]>;
54 Sched<[sched]>;
61 Sched<[sched.Folded, sched.ReadAfterFold]>;
77 Sched<[sched]>;
85 Sched<[sched.Folded, sched.ReadAfterFold]>;
100 Sched<[sched]>;
107 Sched<[sched.Folded, sched.ReadAfterFold]>;
201 Sched<[SchedWriteFShuffle.XMM]>;
208 Sched<[SchedWriteFShuffle.XMM]>;
[all …]
H A DX86InstrFMA.td44 Sched<[sched]>;
53 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>;
64 []>, Sched<[sched]>;
73 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>;
84 []>, Sched<[sched]>;
95 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>;
186 Sched<[sched]>;
195 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>;
206 []>, Sched<[sched]>;
215 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoSFB.td25 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
44 Sched<[]>;
56 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
61 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
66 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
71 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
76 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
81 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
86 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
91 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
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H A DRISCVInstrInfoZa.td135 def WRS_NTO : WRSInst<0b000000001101, "wrs.nto">, Sched<[]>;
136 def WRS_STO : WRSInst<0b000000011101, "wrs.sto">, Sched<[]>;
145 Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
147 Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
149 Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
151 Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
153 Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
155 Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
157 Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
159 Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
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H A DRISCVInstrInfoXTHead.td273 Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
294 Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
318 Sched<[WriteLDW, WriteLDW, ReadMemBase]>;
320 Sched<[WriteSTW, WriteSTW, ReadStoreData, ReadMemBase]>;
323 Sched<[WriteLDW, WriteLDW, ReadMemBase]>;
328 Sched<[WriteLDD, WriteLDD, ReadMemBase]>;
330 Sched<[WriteSTD, WriteSTD, ReadStoreData, ReadMemBase]>;
336 Sched<[WriteLDB, ReadMemBase]>;
338 Sched<[WriteLDB, ReadMemBase]>;
340 Sched<[WriteLDB, ReadMemBase]>;
[all …]
H A DRISCVInstrInfoM.td34 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
36 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
38 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
40 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
45 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
47 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
49 Sched<[WriteIRem, ReadIRem, ReadIRem]>;
51 Sched<[WriteIRem, ReadIRem, ReadIRem]>;
56 Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>;
61 Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
[all …]
H A DRISCVInstrInfoQ.td57 Sched<[WriteFSqrt128, ReadFSqrt128]>;
73 Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
78 Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
82 Sched<[WriteFCvtF128ToF64, ReadFCvtF128ToF64]>;
87 Sched<[WriteFCvtF64ToF128, ReadFCvtF64ToF128]>;
98 Sched<[WriteFClass128, ReadFClass128]>;
103 Sched<[WriteFCvtF128ToI32, ReadFCvtF128ToI32]>;
108 Sched<[WriteFCvtF128ToI32, ReadFCvtF128ToI32]>;
113 Sched<[WriteFCvtI32ToF128, ReadFCvtI32ToF128]>;
118 Sched<[WriteFCvtI32ToF128, ReadFCvtI32ToF128]>;
[all …]
H A DRISCVInstrInfoZb.td272 Sched<[WriteIALU, ReadIALU, ReadIALU]>;
274 Sched<[WriteIALU, ReadIALU, ReadIALU]>;
276 Sched<[WriteIALU, ReadIALU, ReadIALU]>;
281 Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
284 Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
286 Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
291 Sched<[WriteShiftImm32, ReadShiftImm32]>;
293 Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
295 Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
297 Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
[all …]
H A DRISCVInstrInfoZc.td174 Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
178 Sched<[WriteIALU, ReadIALU]>;
180 Sched<[WriteIALU, ReadIALU]>;
182 Sched<[WriteIALU, ReadIALU]>;
187 Sched<[WriteIALU, ReadIALU]>;
191 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
195 Sched<[WriteIALU, ReadIALU]>;
198 Sched<[WriteLDB, ReadMemBase]>;
200 Sched<[WriteLDH, ReadMemBase]>;
202 Sched<[WriteLDH, ReadMemBase]>;
[all …]
H A DRISCVInstrInfoC.td302 Sched<[WriteIALU, ReadIALU]> {
312 Sched<[WriteFLD64, ReadFMemBase]> {
319 Sched<[WriteLDW, ReadMemBase]> {
328 Sched<[WriteLDW, ReadMemBase]> {
338 Sched<[WriteFLD32, ReadFMemBase]> {
347 Sched<[WriteLDD, ReadMemBase]> {
355 Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {
362 Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
371 Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
381 Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
[all …]
H A DRISCVInstrInfoZicbo.td51 def CBO_CLEAN : CBO_r<0b000000000001, "cbo.clean">, Sched<[]>;
52 def CBO_FLUSH : CBO_r<0b000000000010, "cbo.flush">, Sched<[]>;
53 def CBO_INVAL : CBO_r<0b000000000000, "cbo.inval">, Sched<[]>;
57 def CBO_ZERO : CBO_r<0b000000000100, "cbo.zero">, Sched<[]>;
61 def PREFETCH_I : Prefetch_ri<0b00000, "prefetch.i">, Sched<[]>;
62 def PREFETCH_R : Prefetch_ri<0b00001, "prefetch.r">, Sched<[]>;
63 def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>;
H A DRISCVInstrInfoXCV.td377 Sched<[]>;
379 Sched<[]>;
383 Sched<[]>;
385 Sched<[]>;
387 Sched<[]>;
389 Sched<[]>;
393 Sched<[]>;
395 Sched<[]>;
397 Sched<[]>;
399 Sched<[]>;
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H A DRISCVInstrInfoA.td64 defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
66 Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>;
71 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
73 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
75 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
77 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
79 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
81 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
83 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
85 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
[all …]
H A DRISCVInstrInfoZfa.td98 Sched<[WriteFLI32]>;
106 Sched<[WriteFRoundF32, ReadFRoundF32]>;
108 Sched<[WriteFRoundF32, ReadFRoundF32]>;
119 Sched<[WriteFLI64]>;
127 Sched<[WriteFRoundF64, ReadFRoundF64]>;
129 Sched<[WriteFRoundF64, ReadFRoundF64]>;
134 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
145 Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;
147 Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64, ReadFMovI64ToF64]>;
153 Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;
[all …]
H A DRISCVInstrInfoXqccmp.td84 Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;
89 Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;
94 Sched<[WriteIALU, ReadIALU, ReadStoreData, ReadStoreData,
101 Sched<[WriteIALU, WriteIALU, ReadIALU, ReadStoreData, ReadStoreData,
109 Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
116 Sched<[WriteIALU, WriteIALU, WriteLDW, WriteLDW, WriteLDW,
124 Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
H A DRISCVInstrInfo.td622 Sched<[WriteJmp, ReadJmp, ReadJmp]> {
663 Sched<[WriteIALU, ReadIALU]>;
683 opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>;
690 opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR]>;
735 "lui", "$rd, $imm20">, Sched<[WriteIALU]>;
738 "auipc", "$rd, $imm20">, Sched<[WriteIALU]>;
741 "jal", "$rd, $imm20">, Sched<[WriteJal]>;
746 Sched<[WriteJalr, ReadJalr]>;
757 def LB : Load_ri<0b000, "lb">, Sched<[WriteLDB, ReadMemBase]>;
758 def LH : Load_ri<0b001, "lh">, Sched<[WriteLDH, ReadMemBase]>;
[all …]
H A DRISCVInstrInfoXwch.td67 Sched<[WriteLDB, ReadMemBase]> {
78 Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
89 Sched<[WriteLDH, ReadMemBase]> {
98 Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {
108 Sched<[WriteLDB, ReadMemBase]> {
117 Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
126 Sched<[WriteLDH, ReadMemBase]> {
135 Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb.td391 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
404 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
424 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
435 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
456 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
468 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
484 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
493 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
503 [(ARMretglue)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
507 [(ARMseretglue)]>, Sched<[WriteBr]>;
[all …]

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