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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsSVE.def1 //===--- BuiltinsSVE.def - SVE Builtin function database --------*- C++ -*-===//
9 // This file defines the SVE-specific builtin function database. Users of
H A DTargetBuiltins.h47 namespace SVE {
59 LastSVEBuiltin = SVE::FirstTSBuiltin - 1,
73 LastSVEBuiltin = SVE::FirstTSBuiltin - 1,
74 FirstSMEBuiltin = SVE::FirstTSBuiltin,
H A Darm_sve_sme_incl.td1 //===--- arm_sve_sme_incl.td - ARM SVE/SME compiler interface -------------===//
10 // SVE and SME intrinsics.
228 … : FlagType<0x40000000000>; // Use for intrinsics that are common between SVE and SME.
/freebsd/contrib/arm-optimized-routines/
H A DREADME33 math/aarch64/sve - SVE-specific math sources.
75 SVE routines are always built by default - this means that on AArch64
76 GCC >= 10 or LLVM >= 5 are always required for SVE ACLE compatibility.
77 There is no explicit check for compatible compiler, therefore the SVE
H A Dconfig.mk.dist107 # Disable/enable SVE vector math tests/tools.
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td32 // SVE
818 // SVE predicate-as-counter registers
836 // SVE predicate registers
856 // SVE variable-size vector registers
922 // SVE predicate register classes.
933 def PPR_3b : PPRClass<0, 7> { // Restricted 3 bit SVE predicate register class.
941 let Name = "SVE" # name # "Reg";
979 // SVE predicate-as-counter operand
981 let Name = "SVE" # name # "Reg";
1038 let Name = "SVE" # name # "Reg";
[all …]
H A DAArch64SchedPredNeoverse.td36 // Check if SVE INC/DEC (scalar), ALL, {1, 2, 4}
H A DSVEInstrFormats.td1 //=-- SVEInstrFormats.td - AArch64 SVE Instruction classes -*- tablegen -*--=//
9 // AArch64 Scalable Vector Extension (SVE) Instruction Class Definitions.
210 let Name = "SVE" # Infix # "Imm" # ElementWidth;
352 // SVE PTrue - These are used extensively throughout the pattern matching so
411 // SVE pattern match helpers.
623 // SVE pattern match helpers.
731 // SVE Predicate Misc Group
841 // SVE Predicate Count Group
1065 // SVE Element Count Group
1280 // SVE Permute - Cross Lane Group
[all …]
H A DAArch64SchedA510.td56 def CortexA510UnitVALU0 : ProcResource<1>; // SIMD/FP/SVE ALU0
57 def CortexA510UnitVALU1 : ProcResource<1>; // SIMD/FP/SVE ALU0
58 def CortexA510UnitVMAC : ProcResource<2>; // SIMD/FP/SVE MAC
59 …def CortexA510UnitVMC : ProcResource<1>; // SIMD/FP/SVE multicycle instrs (e.g Div, SQRT, c…
541 // SVE Predicate instructions
632 // SVE integer instructions
996 // SVE floating-point instructions
1153 // SVE BFloat16 (BF16) instructions
1168 // SVE Load instructions
1268 // SVE Store instructions
[all …]
H A DAArch64SchedNeoverseN2.td1497 // SVE Predicate instructions
1576 // SVE integer instructions
1914 // SVE floating-point instructions
2070 // SVE BFloat16 (BF16) instructions
2085 // SVE Load instructions
2184 // SVE Store instructions
2277 // SVE Miscellaneous instructions
2296 // SVE Cryptographic instructions
H A DAArch64SchedNeoverseV1.td1306 // SVE Predicate instructions
1369 // SVE integer instructions
1552 // SVE floating-point instructions
1677 // SVE BFloat16 (BF16) instructions
1693 // SVE Load instructions
1789 // SVE Store instructions
1860 // SVE Miscellaneous instructions
H A DAArch64Features.td158 def FeatureSVE : ExtensionWithMArch<"sve", "SVE", "FEAT_SVE",
159 "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>;
419 "Enable the full A64 instruction set in streaming SVE mode", [FeatureSME, FeatureSVE2]>;
H A DAArch64SchedNeoverseV2.td2003 // SVE Predicate instructions
2085 // SVE integer instructions
2431 // SVE floating-point instructions
2590 // SVE BFloat16 (BF16) instructions
2605 // SVE Load instructions
2707 // SVE Store instructions
2792 // SVE Miscellaneous instructions
2812 // SVE Cryptographic instructions
H A DAArch64CallingConvention.td598 // Functions taking SVE arguments or returning an SVE type
H A DAArch64SystemOperands.td285 // SVE Prefetch instruction options.
334 // SVE Predicate patterns
365 // SVE Predicate-as-counter patterns
823 // SVE control registers
1625 // SVE control registers
H A DAArch64SVEInstrInfo.td1 //=- AArch64SVEInstrInfo.td - AArch64 SVE Instructions -*- tablegen -*-----=//
9 // AArch64 Scalable Vector Extension (SVE) Instruction definitions.
25 // distinguish predicated from unpredicated nodes given that most SVE
140 // AArch64 SVE/SVE2 - the remaining node definitions
143 // SVE CNT/INC/RDVL
149 // SVE DEC
580 // SVE predicated integer reductions.
790 // SVE floating point reductions.
1903 // Extract subvectors from FP SVE vectors
4103 // Aliases for existing SVE instructions for which predicate-as-counter are
H A DAArch64FrameLowering.cpp723 bool SVE) { in emitCalleeSavedRestores() argument
737 if (SVE != in emitCalleeSavedRestores()
742 if (SVE && in emitCalleeSavedRestores()
H A DAArch64Processors.td899 // Historically, llvm defined v9.0a as requiring SVE, but it's optional
H A DAArch64SchedA64FX.td2052 // SVE instructions
2054 // The modeling method for SVE instructions is more accurate than others.
/freebsd/contrib/arm-optimized-routines/math/tools/
H A Dexp10.sollya8 N = 1; // Neon 1, SVE 64
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp7498 #NameBase, SVE::BI__builtin_sve_##NameBase, Intrinsic::LLVMIntrinsic, 0, \
7503 { #NameBase, SVE::BI__builtin_sve_##NameBase, 0, 0, TypeModifier }
10473 if (BuiltinID >= SVE::BI__builtin_sve_reinterpret_s8_s8 && in EmitAArch64SVEBuiltinExpr()
10474 BuiltinID <= SVE::BI__builtin_sve_reinterpret_f64_f64_x4) { in EmitAArch64SVEBuiltinExpr()
10569 case SVE::BI__builtin_sve_svreinterpret_b: { in EmitAArch64SVEBuiltinExpr()
10576 case SVE::BI__builtin_sve_svreinterpret_c: { in EmitAArch64SVEBuiltinExpr()
10584 case SVE::BI__builtin_sve_svpsel_lane_b8: in EmitAArch64SVEBuiltinExpr()
10585 case SVE::BI__builtin_sve_svpsel_lane_b16: in EmitAArch64SVEBuiltinExpr()
10586 case SVE::BI__builtin_sve_svpsel_lane_b32: in EmitAArch64SVEBuiltinExpr()
10587 case SVE::BI__builtin_sve_svpsel_lane_b64: in EmitAArch64SVEBuiltinExpr()
[all …]
/freebsd/contrib/llvm-project/clang/utils/TableGen/
H A DSveEmitter.cpp47 enum class ACLEKind { SVE, SME }; enumerator
1098 case ACLEKind::SVE: in emitIntrinsic()
1423 createCoreHeaderIntrinsics(OS, *this, ACLEKind::SVE); in createHeader()
1798 case ACLEKind::SVE: in createStreamingAttrs()
1862 SVEEmitter(Records).createStreamingAttrs(OS, ACLEKind::SVE); in EmitSveStreamingAttrs()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DVFABIDemangling.cpp
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td1433 // SVE
2695 // SVE ACLE: 7.3. INT8 matrix multiply extensions
2706 // SVE ACLE: 7.4/5. FP64/FP32 matrix multiply extensions
2711 // SVE ACLE: 7.2. BFloat16 extensions
/freebsd/sys/arm64/arm64/
H A Didentcpu.c1512 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SVE, NONE, IMPL),
1593 MRS_FIELD_HWCAP(ID_AA64PFR0, SVE, false, MRS_LOWER,

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