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Searched refs:ST1 (Results 1 – 25 of 29) sorted by relevance

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/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_cyclone5_mercury_sa1_st1_emmc.dts13 model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board";
H A Dsocfpga_arria10_mercury_aa1_st1_sdmmc.dts13 model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board";
H A Dsocfpga_cyclone5_mercury_sa1_st1_qspi.dts13 model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board";
H A Dsocfpga_arria10_mercury_aa1_st1_qspi.dts13 model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board";
H A Dsocfpga_cyclone5_mercury_sa2_st1_qspi.dts13 model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board";
H A Dsocfpga_cyclone5_mercury_sa1_st1_sdmmc.dts13 model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board";
H A Dsocfpga_cyclone5_mercury_sa2_st1_sdmmc.dts13 model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board";
H A Dsocfpga_arria10_mercury_aa1_st1_emmc.dts13 model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board";
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAsmAlias.td552 // Various unary fpstack operations default to operating on ST1.
554 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
555 def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>;
556 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
557 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
558 def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>;
559 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
560 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
561 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
562 def : InstAlias<"fxch", (XCH_F ST1), 0>;
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H A DX86InstrControl.td20 // ST1 arguments when returning values on the x87 stack.
H A DX86InstrMMX.td153 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
H A DX86RegisterInfo.td446 def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>;
H A DX86InstrCompiler.td483 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
503 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp208 {codeview::RegisterId::ST1, X86::ST1}, in initLLVMToSEHAndCVRegMapping()
217 {codeview::RegisterId::ST1, X86::FP1}, in initLLVMToSEHAndCVRegMapping()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td993 (instregex "^ST1(One(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64)|One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))$")>;
995 (instregex "^ST1(One(v8b|v4h|v2s|v1d)_POST|(i8|i16|i32|i64)_POST)$")>;
999 (instregex "^ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>;
1004 (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>;
1013 (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>;
H A DAArch64SchedKryoDetails.td1848 (instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))$")>;
1854 …(instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))_POST$…
1860 (instregex "ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>;
1866 (instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>;
1872 (instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>;
H A DAArch64InstrInfo.td4510 // We must use ST1 to store vectors in big-endian.
4524 // We must use ST1 to store vectors in big-endian.
4612 // We must use ST1 to store vectors in big-endian.
4639 // We must use ST1 to store vectors in big-endian.
4763 // We must use ST1 to store vectors in big-endian.
4789 // We must use ST1 to store vectors in big-endian.
4978 // We must use ST1 to store vectors in big-endian.
8933 defm ST1 : SIMDSt1Multiple<"st1">;
9152 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
9153 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
[all …]
H A DAArch64SchedA510.td1278 def : InstRW<[CortexA510VSt0], (instregex "^ST1[BHWD]_IMM$",
1285 def : InstRW<[CortexA510VSt0], (instregex "^ST1[BWD]$",
H A DAArch64SchedA320.td1300 def : InstRW<[CortexA320VSt0], (instregex "^ST1[BHWD]_IMM$",
1307 def : InstRW<[CortexA320VSt0], (instregex "^ST1[BWD]$",
H A DAArch64SchedNeoverseV1.td1922 def : InstRW<[V1Write_2c_1L01_1V], (instregex "^ST1[BHWD]_IMM$",
1926 "^ST1[BWD]$",
H A DAArch64SchedNeoverseN2.td2235 def : InstRW<[N2Write_2c_1L01_1V], (instregex "^ST1[BHWD]_IMM$",
2242 def : InstRW<[N2Write_2c_1L01_1V], (instregex "^ST1[BWD]$",
H A DAArch64SchedNeoverseN3.td2210 def : InstRW<[N3Write_2c_1L01_1V], (instregex "^ST1[BHWD]_IMM$",
2219 def : InstRW<[N3Write_2c_1L01_1V], (instregex "^ST1[BWD]$",
H A DAArch64SchedNeoverseV2.td2734 def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^ST1[BHWD]_IMM$",
2741 def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^ST1[BWD]$",
/freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def126 CV_REGISTER(ST1, 129)
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp22624 if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) { in visitSTORE() local
22626 ST1->isUnindexed() && ST1->isSimple()) { in visitSTORE()
22627 if (OptLevel != CodeGenOptLevel::None && ST1->getBasePtr() == Ptr && in visitSTORE()
22628 ST1->getValue() == Value && ST->getMemoryVT() == ST1->getMemoryVT() && in visitSTORE()
22629 ST->getAddressSpace() == ST1->getAddressSpace()) { in visitSTORE()
22635 if (OptLevel != CodeGenOptLevel::None && ST1->hasOneUse() && in visitSTORE()
22636 !ST1->getBasePtr().isUndef() && in visitSTORE()
22637 ST->getAddressSpace() == ST1->getAddressSpace()) { in visitSTORE()
22643 ST1->getMemoryVT().isScalableVector()) { in visitSTORE()
22644 if (ST1->getBasePtr() == Ptr && in visitSTORE()
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