| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 82 for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid(); in initReg() local
83 ++SRI) in initReg()
84 if (RI.subregs(*SRI).empty()) in initReg()
86 Uses.insert(*SRI); in initReg()
148 for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid(); in init() local
149 ++SRI) { in init()
150 if (!RI.subregs(*SRI).empty()) in init()
154 if (R == *SRI) { in init()
163 if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI) in init()
168 SoftDefs.insert(*SRI); in init()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 121 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
123 if (*SRI == Idx) in getSubReg()
125 ++SRI; in getSubReg()
135 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
138 return *SRI; in getSubRegIndex()
139 ++SRI; in getSubRegIndex()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 144 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf) in computeConcatTransitiveClosure()
145 assert(SRI->ConcatenationOf.empty() && "No transitive closure?"); in computeConcatTransitiveClosure()
181 for (const auto &[SRI, SR] : zip_equal(SRIs, SRs)) { in buildObjectGraph()
182 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRI)); in buildObjectGraph()
266 SubRegMap::const_iterator SRI = Map.find(Key); in computeSubRegs() local
267 if (SRI == Map.end()) in computeSubRegs()
271 if (SubRegs.count(Val) || !Orphans.erase(SRI->second)) in computeSubRegs()
274 SubRegs.try_emplace(Val, SRI->second); in computeSubRegs()
299 for (const auto &[SRI, SubReg] : Map) in computeSubRegs()
301 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SRI)] = SubReg; in computeSubRegs()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyCFGSort.cpp | 222 SortRegionInfo SRI(MLI, WEI); in sortBlocks() local
225 const SortRegion *R = SRI.getRegionFor(MBB); in sortBlocks()
344 const SortRegion *Region = SRI.getRegionFor(&MBB); in sortBlocks()
370 assert(OnStack.count(SRI.getRegionFor(&MBB)) && in sortBlocks()
373 while (OnStack.size() > 1 && &MBB == SRI.getBottom(OnStack.back())) in sortBlocks()
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| H A D | WebAssemblyCFGStackify.cpp | 438 SortRegionInfo SRI(MLI, WEI); in placeLoopMarker() local
447 MachineBasicBlock *Bottom = SRI.getBottom(Loop); in placeLoopMarker()
508 SortRegionInfo SRI(MLI, WEI); in placeTryMarker() local
528 MachineBasicBlock *Bottom = SRI.getBottom(WE); in placeTryMarker()
702 SortRegionInfo SRI(MLI, WEI); in placeTryTableMarker() local
723 MachineBasicBlock *Bottom = SRI.getBottom(WE); in placeTryTableMarker()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | VirtRegMap.cpp | 393 LiveInterval::const_iterator &SRI = RangeIterPair.second; in addLiveInsForSubRanges() local
394 while (SRI != SR->end() && SRI->end <= MBBBegin) in addLiveInsForSubRanges()
395 ++SRI; in addLiveInsForSubRanges()
396 if (SRI == SR->end()) in addLiveInsForSubRanges()
398 if (SRI->start <= MBBBegin) in addLiveInsForSubRanges()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 285 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
308 for (auto [SubReg, SRI] : SubRegs) in getMinSizeReg()
312 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
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| H A D | GCNSchedStrategy.cpp | 169 ScheduleDAGMI *DAG, const SIRegisterInfo *SRI) { in getRegisterPressures() argument
187 NewPressure = TempDownwardTracker.bumpDownwardPressure(MI, SRI); in getRegisterPressures()
202 const SIRegisterInfo *SRI, in initCandidate() argument
227 DownwardTracker, UpwardTracker, DAG, SRI); in initCandidate()
246 DownwardTracker, UpwardTracker, DAG, SRI); in initCandidate()
329 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo *>(TRI); in pickNodeFromQueue() local
349 initCandidate(TryCand, SU, Zone.isTop(), RPTracker, SRI, SGPRPressure, in pickNodeFromQueue()
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| H A D | GCNRegPressure.cpp | 409 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo *>(TRI); in isSaveBeneficial() local
411 if (SRI->isSGPRClass(RC)) in isSaveBeneficial()
414 SRI->isAGPRClass(RC) ? RP.getAGPRNum() : RP.getArchVGPRNum(); in isSaveBeneficial()
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| H A D | GCNSchedStrategy.h | 55 const SIRegisterInfo *SRI, unsigned SGPRPressure,
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| /freebsd/sys/dev/xilinx/ |
| H A D | axidma_if.m | 4 # This software was developed by SRI International and the University of
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| /freebsd/sys/dev/gpio/dwgpio/ |
| H A D | dwgpio_if.m | 4 # This software was developed by SRI International and the University of
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| /freebsd/sys/dts/arm/ |
| H A D | tegra124-jetson-tk1-fbsd.dts | 5 * This software was developed by SRI International and the University of
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 1912 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump() local
1913 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1914 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; in debugDump()
1915 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; in debugDump()
1918 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Offset; in debugDump()
1921 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Size; in debugDump()
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| /freebsd/sys/arm64/coresight/ |
| H A D | coresight_if.m | 5 # This software was developed by SRI International and the University of
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| /freebsd/sys/dev/flash/ |
| H A D | qspi_if.m | 5 # This software was developed by SRI International and the University of
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| /freebsd/sys/dev/xdma/ |
| H A D | xdma_if.m | 5 # This software was developed by SRI International and the University of
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| /freebsd/sys/arm64/iommu/ |
| H A D | iommu_if.m | 6 # This software was developed by SRI International and the University of
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| /freebsd/sbin/pfctl/tests/ |
| H A D | pfctl_test_list.inc | 6 * This software was developed by SRI International and the University of
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | InstrRefBasedImpl.cpp | 1997 for (MCSubRegIndexIterator SRI(SrcRegNum, TRI); SRI.isValid(); ++SRI) { in performCopy() local
1998 unsigned SrcSubReg = SRI.getSubReg(); in performCopy()
1999 unsigned SubRegIdx = SRI.getSubRegIndex(); in performCopy()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/ |
| H A D | GlobalISelMatchTable.h | 2188 SubRegIndexRenderer(unsigned InsnID, const CodeGenSubRegIndex *SRI) in SubRegIndexRenderer() argument
2189 : OperandRenderer(OR_SubRegIndex), InsnID(InsnID), SubRegIdx(SRI) {} in SubRegIndexRenderer()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 5894 unsigned SRI; in Select() local
5897 case 0: SRI = PPC::sub_lt; break; in Select()
5898 case 1: SRI = PPC::sub_gt; break; in Select()
5899 case 2: SRI = PPC::sub_eq; break; in Select()
5900 case 3: SRI = PPC::sub_un; break; in Select()
5903 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg); in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedCyclone.td | 501 // SLI,SRI
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| H A D | AArch64SchedNeoverseV2.td | 1534 def : InstRW<[V2Write_2c_1V13], (instregex "^SLI[dv]", "^SRI[dv]")>;
2168 def : InstRW<[V2Write_2c_1V13], (instregex "^(SLI|SRI)_ZZI_[BHSD]")>;
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| H A D | AArch64SchedA510.td | 707 (instregex "^(SHRNB|SHRNT|SSHLLB|SSHLLT|USHLLB|USHLLT|SLI|SRI)_ZZI_[BHSD]")>;
|