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Searched refs:SRI (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp82 for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid(); in initReg() local
83 ++SRI) in initReg()
84 if (RI.subregs(*SRI).empty()) in initReg()
86 Uses.insert(*SRI); in initReg()
148 for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid(); in init() local
149 ++SRI) { in init()
150 if (!RI.subregs(*SRI).empty()) in init()
154 if (R == *SRI) { in init()
163 if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI) in init()
168 SoftDefs.insert(*SRI); in init()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp121 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
123 if (*SRI == Idx) in getSubReg()
125 ++SRI; in getSubReg()
135 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
138 return *SRI; in getSubRegIndex()
139 ++SRI; in getSubRegIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp228 for (auto &[OldSubReg, SRI] : SubRegs) { in getRegClassWithShiftedSubregs()
229 auto &[SubRegRC, NewSubReg] = SRI; in getRegClassWithShiftedSubregs()
283 for (auto [SubReg, SRI] : SubRegs) in getRegClassWithShiftedSubregs()
285 assert(MinRC == TRI->getSubClassWithSubReg(MinRC, SRI.SubReg)); in getRegClassWithShiftedSubregs()
299 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
323 for (auto [SubReg, SRI] : SubRegs) in getMinSizeReg()
327 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
H A DAMDGPUMachineCFGStructurizer.cpp2056 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2057 unsigned SourceReg = (*SRI).first; in prunePHIInfo()
2067 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2068 PHILinearize::PHISourceT Source = *SRI; in prunePHIInfo()
2099 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2104 auto SRI = PHIInfo.sources_begin(DestReg); in createEntryPHI() local
2105 unsigned SourceReg = (*SRI).first; in createEntryPHI()
2115 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2116 unsigned SourceReg = (*SRI).first; in createEntryPHI()
2118 if (CurrentRegion->contains((*SRI).second)) { in createEntryPHI()
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H A DGCNSchedStrategy.cpp167 const SIRegisterInfo *SRI, in initCandidate() argument
292 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI); in pickNodeFromQueue() local
304 initCandidate(TryCand, SU, Zone.isTop(), RPTracker, SRI, SGPRPressure, in pickNodeFromQueue()
1372 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo *>(DAG.TRI); in collectRematerializableInstructions() local
1379 if (!SRI->isVGPRClass(DAG.MRI.getRegClass(Reg)) || in collectRematerializableInstructions()
H A DGCNSchedStrategy.h52 const SIRegisterInfo *SRI, unsigned SGPRPressure,
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyCFGSort.cpp223 SortRegionInfo SRI(MLI, WEI); in sortBlocks() local
226 const SortRegion *R = SRI.getRegionFor(MBB); in sortBlocks()
344 const SortRegion *Region = SRI.getRegionFor(&MBB); in sortBlocks()
370 assert(OnStack.count(SRI.getRegionFor(&MBB)) && in sortBlocks()
373 while (OnStack.size() > 1 && &MBB == SRI.getBottom(OnStack.back())) in sortBlocks()
H A DWebAssemblyCFGStackify.cpp401 SortRegionInfo SRI(MLI, WEI); in placeLoopMarker() local
410 MachineBasicBlock *Bottom = SRI.getBottom(Loop); in placeLoopMarker()
471 SortRegionInfo SRI(MLI, WEI); in placeTryMarker() local
491 MachineBasicBlock *Bottom = SRI.getBottom(WE); in placeTryMarker()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DVirtRegMap.cpp323 LiveInterval::const_iterator &SRI = RangeIterPair.second; in addLiveInsForSubRanges() local
324 while (SRI != SR->end() && SRI->end <= MBBBegin) in addLiveInsForSubRanges()
325 ++SRI; in addLiveInsForSubRanges()
326 if (SRI == SR->end()) in addLiveInsForSubRanges()
328 if (SRI->start <= MBBBegin) in addLiveInsForSubRanges()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp142 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf) in computeConcatTransitiveClosure()
143 assert(SRI->ConcatenationOf.empty() && "No transitive closure?"); in computeConcatTransitiveClosure()
328 SubRegMap::const_iterator SRI = Map.find(Comp.first); in computeSubRegs() local
329 if (SRI == Map.end()) in computeSubRegs()
333 if (SubRegs.count(Comp.second) || !Orphans.erase(SRI->second)) in computeSubRegs()
336 SubRegs.insert(std::pair(Comp.second, SRI->second)); in computeSubRegs()
1258 for (CodeGenSubRegIndex &SRI : SubRegIndices) { in CodeGenRegBank()
1259 SRI.computeConcatTransitiveClosure(); in CodeGenRegBank()
1260 if (!SRI.ConcatenationOf.empty()) in CodeGenRegBank()
1263 SRI.ConcatenationOf.begin(), SRI.ConcatenationOf.end()), in CodeGenRegBank()
[all …]
/freebsd/sys/dev/gpio/dwgpio/
H A Ddwgpio_if.m4 # This software was developed by SRI International and the University of
/freebsd/sys/dts/arm/
H A Dtegra124-jetson-tk1-fbsd.dts5 * This software was developed by SRI International and the University of
H A Dsocfpga_cyclone5_sockit_sdmmc.dts5 * This software was developed by SRI International and the University of
H A Dsocfpga_arria10_socdk_sdmmc.dts5 * This software was developed by SRI International and the University of
H A Dsocfpga_cyclone5_sockit_beri_sdmmc.dts5 * This software was developed by SRI International and the University of
/freebsd/sys/arm64/coresight/
H A Dcoresight_if.m5 # This software was developed by SRI International and the University of
/freebsd/sys/dev/altera/pio/
H A Dpio_if.m5 # This software was developed by SRI International and the University of
/freebsd/sys/dev/flash/
H A Dqspi_if.m5 # This software was developed by SRI International and the University of
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp1866 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump() local
1867 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1868 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; in debugDump()
1869 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; in debugDump()
1872 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Offset; in debugDump()
1875 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Size; in debugDump()
/freebsd/sys/dev/virtio/mmio/
H A Dvirtio_mmio_if.m5 # This software was developed by SRI International and the University of
/freebsd/sys/dev/xdma/
H A Dxdma_if.m5 # This software was developed by SRI International and the University of
/freebsd/sys/arm64/iommu/
H A Diommu_if.m6 # This software was developed by SRI International and the University of
/freebsd/sbin/pfctl/tests/
H A Dpfctl_test_list.inc6 * This software was developed by SRI International and the University of
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
H A DInstrRefBasedImpl.cpp1963 for (MCSubRegIndexIterator SRI(SrcRegNum, TRI); SRI.isValid(); ++SRI) { in performCopy() local
1964 unsigned SrcSubReg = SRI.getSubReg(); in performCopy()
1965 unsigned SubRegIdx = SRI.getSubRegIndex(); in performCopy()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/
H A DGlobalISelMatchTable.h2127 SubRegIndexRenderer(unsigned InsnID, const CodeGenSubRegIndex *SRI) in SubRegIndexRenderer() argument
2128 : OperandRenderer(OR_SubRegIndex), InsnID(InsnID), SubRegIdx(SRI) {} in SubRegIndexRenderer()

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