185debf7fSRuslan Bukin#- 2951e0584SRuslan Bukin# Copyright (c) 2016-2019 Ruslan Bukin <br@bsdpad.com> 385debf7fSRuslan Bukin# All rights reserved. 485debf7fSRuslan Bukin# 585debf7fSRuslan Bukin# This software was developed by SRI International and the University of 685debf7fSRuslan Bukin# Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 785debf7fSRuslan Bukin# ("CTSRD"), as part of the DARPA CRASH research programme. 885debf7fSRuslan Bukin# 985debf7fSRuslan Bukin# Redistribution and use in source and binary forms, with or without 1085debf7fSRuslan Bukin# modification, are permitted provided that the following conditions 1185debf7fSRuslan Bukin# are met: 1285debf7fSRuslan Bukin# 1. Redistributions of source code must retain the above copyright 1385debf7fSRuslan Bukin# notice, this list of conditions and the following disclaimer. 1485debf7fSRuslan Bukin# 2. Redistributions in binary form must reproduce the above copyright 1585debf7fSRuslan Bukin# notice, this list of conditions and the following disclaimer in the 1685debf7fSRuslan Bukin# documentation and/or other materials provided with the distribution. 1785debf7fSRuslan Bukin# 1885debf7fSRuslan Bukin# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1985debf7fSRuslan Bukin# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2085debf7fSRuslan Bukin# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2185debf7fSRuslan Bukin# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2285debf7fSRuslan Bukin# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2385debf7fSRuslan Bukin# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2485debf7fSRuslan Bukin# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2585debf7fSRuslan Bukin# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2685debf7fSRuslan Bukin# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2785debf7fSRuslan Bukin# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2885debf7fSRuslan Bukin# SUCH DAMAGE. 2985debf7fSRuslan Bukin# 3085debf7fSRuslan Bukin# 3185debf7fSRuslan Bukin 3247218e71SAndrew Turner#include "opt_platform.h" 3347218e71SAndrew Turner 34*91e2614aSAndrew Turner#include <sys/malloc.h> 35*91e2614aSAndrew Turner 3685debf7fSRuslan Bukin#include <machine/bus.h> 3785debf7fSRuslan Bukin 3885debf7fSRuslan Bukin#ifdef FDT 3985debf7fSRuslan Bukin#include <dev/fdt/fdt_common.h> 4085debf7fSRuslan Bukin#include <dev/ofw/ofw_bus.h> 4185debf7fSRuslan Bukin#include <dev/ofw/ofw_bus_subr.h> 4285debf7fSRuslan Bukin#endif 4385debf7fSRuslan Bukin 4485debf7fSRuslan Bukin#include <dev/xdma/xdma.h> 4585debf7fSRuslan Bukin 4685debf7fSRuslan BukinINTERFACE xdma; 4785debf7fSRuslan Bukin 4885debf7fSRuslan Bukin# 493d5b3b0aSRuslan Bukin# Request a transfer. 5085debf7fSRuslan Bukin# 513d5b3b0aSRuslan BukinMETHOD int channel_request { 523d5b3b0aSRuslan Bukin device_t dev; 533d5b3b0aSRuslan Bukin struct xdma_channel *xchan; 543d5b3b0aSRuslan Bukin struct xdma_request *req; 553d5b3b0aSRuslan Bukin}; 563d5b3b0aSRuslan Bukin 573d5b3b0aSRuslan Bukin# 583d5b3b0aSRuslan Bukin# Prepare xDMA channel for a scatter-gather transfer. 593d5b3b0aSRuslan Bukin# 603d5b3b0aSRuslan BukinMETHOD int channel_prep_sg { 6185debf7fSRuslan Bukin device_t dev; 6285debf7fSRuslan Bukin struct xdma_channel *xchan; 6385debf7fSRuslan Bukin}; 6485debf7fSRuslan Bukin 6585debf7fSRuslan Bukin# 663d5b3b0aSRuslan Bukin# Query DMA engine driver for the amount of free entries 673d5b3b0aSRuslan Bukin# (descriptors) are available. 6885debf7fSRuslan Bukin# 693d5b3b0aSRuslan BukinMETHOD int channel_capacity { 7085debf7fSRuslan Bukin device_t dev; 7185debf7fSRuslan Bukin struct xdma_channel *xchan; 723d5b3b0aSRuslan Bukin uint32_t *capacity; 733d5b3b0aSRuslan Bukin}; 743d5b3b0aSRuslan Bukin 753d5b3b0aSRuslan Bukin# 763d5b3b0aSRuslan Bukin# Submit sglist list to DMA engine driver. 773d5b3b0aSRuslan Bukin# 783d5b3b0aSRuslan BukinMETHOD int channel_submit_sg { 793d5b3b0aSRuslan Bukin device_t dev; 803d5b3b0aSRuslan Bukin struct xdma_channel *xchan; 813d5b3b0aSRuslan Bukin struct xdma_sglist *sg; 823d5b3b0aSRuslan Bukin uint32_t sg_n; 8385debf7fSRuslan Bukin}; 8485debf7fSRuslan Bukin 85*91e2614aSAndrew Turner#ifdef FDT 8685debf7fSRuslan Bukin# 8785debf7fSRuslan Bukin# Notify driver we have machine-dependend data. 8885debf7fSRuslan Bukin# 8985debf7fSRuslan BukinMETHOD int ofw_md_data { 9085debf7fSRuslan Bukin device_t dev; 9185debf7fSRuslan Bukin pcell_t *cells; 9285debf7fSRuslan Bukin int ncells; 9385debf7fSRuslan Bukin void **data; 9485debf7fSRuslan Bukin}; 95*91e2614aSAndrew Turner#endif 9685debf7fSRuslan Bukin 9785debf7fSRuslan Bukin# 9885debf7fSRuslan Bukin# Allocate both virtual and harware channels. 9985debf7fSRuslan Bukin# 10085debf7fSRuslan BukinMETHOD int channel_alloc { 10185debf7fSRuslan Bukin device_t dev; 10285debf7fSRuslan Bukin struct xdma_channel *xchan; 10385debf7fSRuslan Bukin}; 10485debf7fSRuslan Bukin 10585debf7fSRuslan Bukin# 1063d5b3b0aSRuslan Bukin# Free the real hardware channel. 10785debf7fSRuslan Bukin# 10885debf7fSRuslan BukinMETHOD int channel_free { 10985debf7fSRuslan Bukin device_t dev; 11085debf7fSRuslan Bukin struct xdma_channel *xchan; 11185debf7fSRuslan Bukin}; 11285debf7fSRuslan Bukin 11385debf7fSRuslan Bukin# 11485debf7fSRuslan Bukin# Begin, pause or terminate the channel operation. 11585debf7fSRuslan Bukin# 11685debf7fSRuslan BukinMETHOD int channel_control { 11785debf7fSRuslan Bukin device_t dev; 11885debf7fSRuslan Bukin struct xdma_channel *xchan; 11985debf7fSRuslan Bukin int cmd; 12085debf7fSRuslan Bukin}; 121951e0584SRuslan Bukin 122951e0584SRuslan Bukin# IOMMU interface 123951e0584SRuslan Bukin 124951e0584SRuslan Bukin# 125951e0584SRuslan Bukin# pmap is initialized 126951e0584SRuslan Bukin# 127951e0584SRuslan BukinMETHOD int iommu_init { 128951e0584SRuslan Bukin device_t dev; 129951e0584SRuslan Bukin struct xdma_iommu *xio; 130951e0584SRuslan Bukin}; 131951e0584SRuslan Bukin 132951e0584SRuslan Bukin# 133951e0584SRuslan Bukin# pmap is released 134951e0584SRuslan Bukin# 135951e0584SRuslan BukinMETHOD int iommu_release { 136951e0584SRuslan Bukin device_t dev; 137951e0584SRuslan Bukin struct xdma_iommu *xio; 138951e0584SRuslan Bukin}; 139951e0584SRuslan Bukin 140951e0584SRuslan Bukin# 141951e0584SRuslan Bukin# Mapping entered 142951e0584SRuslan Bukin# 143951e0584SRuslan BukinMETHOD int iommu_enter { 144951e0584SRuslan Bukin device_t dev; 145951e0584SRuslan Bukin struct xdma_iommu *xio; 146951e0584SRuslan Bukin vm_offset_t va; 147951e0584SRuslan Bukin vm_offset_t pa; 148951e0584SRuslan Bukin}; 149951e0584SRuslan Bukin 150951e0584SRuslan Bukin# 151951e0584SRuslan Bukin# Mapping removed 152951e0584SRuslan Bukin# 153951e0584SRuslan BukinMETHOD int iommu_remove { 154951e0584SRuslan Bukin device_t dev; 155951e0584SRuslan Bukin struct xdma_iommu *xio; 156951e0584SRuslan Bukin vm_offset_t va; 157951e0584SRuslan Bukin}; 158