Home
last modified time | relevance | path

Searched refs:SPReg (Results 1 – 25 of 34) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.cpp89 Register SPReg = CSKY::R14; in emitPrologue() local
117 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -(static_cast<int64_t>(ActualSize)), in emitPrologue()
152 .addReg(SPReg) in emitPrologue()
162 adjustReg(MBB, MBBI, DL, SPReg, SPReg, in emitPrologue()
173 BuildMI(MBB, MBBI, DL, TII->get(CSKY::ANDNI32), SPReg) in emitPrologue()
174 .addReg(SPReg) in emitPrologue()
183 .addReg(SPReg) in emitPrologue()
185 BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSLI32), SPReg) in emitPrologue()
191 BuildMI(MBB, MBBI, DL, TII->get(CSKY::MOV16), VR).addReg(SPReg); in emitPrologue()
198 BuildMI(MBB, MBBI, DL, TII->get(CSKY::MOV16), SPReg).addReg(VR); in emitPrologue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFrameLowering.cpp189 Register SPReg = LoongArch::R3; in emitPrologue() local
216 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup); in emitPrologue()
245 adjustReg(MBB, MBBI, DL, FPReg, SPReg, in emitPrologue()
263 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount, in emitPrologue()
285 SPReg) in emitPrologue()
286 .addReg(SPReg) in emitPrologue()
298 .addReg(SPReg) in emitPrologue()
311 Register SPReg = LoongArch::R3; in emitEpilogue() local
331 adjustReg(MBB, LastFrameDestroy, DL, SPReg, LoongArch::R22, in emitEpilogue()
342 adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount, in emitEpilogue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp284 unsigned SPReg = getSPReg(MF); in emitPrologue()
286 SPReg = MRI.createVirtualRegister(PtrRC); in emitPrologue()
290 BuildMI(MBB, InsertPt, DL, TII->get(getOpcGlobGet(MF)), SPReg) in emitPrologue()
299 .addReg(SPReg); in emitPrologue()
307 .addReg(SPReg) in emitPrologue()
347 unsigned SPReg = 0; in emitEpilogue()
351 SPReg = FI->getBasePointerVreg(); in emitEpilogue()
361 SPReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue()
362 BuildMI(MBB, InsertPt, DL, TII->get(getOpcAdd(MF)), SPReg) in emitEpilogue()
366 SPReg in isSupportedStackID()
276 unsigned SPReg = getSPReg(MF); emitPrologue() local
339 unsigned SPReg = 0; emitEpilogue() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp652 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1; in emitPrologue() local
814 .addReg(SPReg); in emitPrologue()
828 .addReg(SPReg); in emitPrologue()
833 .addReg(SPReg); in emitPrologue()
838 .addReg(SPReg); in emitPrologue()
849 .addReg(SPReg); in emitPrologue()
867 .addReg(SPReg); in emitPrologue()
880 .addReg(SPReg); in emitPrologue()
896 .addReg(SPReg) in emitPrologue()
897 .addReg(SPReg); in emitPrologue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp418 const Register SPReg = getSPReg(STI); in adjustStackForRVV() local
439 RI.adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset, in adjustStackForRVV()
534 Register SPReg = getSPReg(STI); in emitPrologue() local
598 if (STI.isRegisterReservedByUser(SPReg)) in emitPrologue()
622 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, in emitPrologue()
669 RI->adjustReg(MBB, MBBI, DL, FPReg, SPReg, in emitPrologue()
687 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, in emitPrologue()
709 *RI, SPReg, getStackSizeWithRVVPadding(MF), RVVStackSize / 8)); in emitPrologue()
727 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg) in emitPrologue()
728 .addReg(SPReg) in emitPrologue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp136 unsigned SPReg = MI.getOperand(0).getReg(); in sandboxLoadStoreStackChange() local
137 assert((Mips::SP == SPReg) && "Unexpected stack-pointer register."); in sandboxLoadStoreStackChange()
138 emitMask(SPReg, LoadStoreStackMaskReg, STI); in sandboxLoadStoreStackChange()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IndirectThunks.cpp235 const Register SPReg = Is64Bit ? X86::RSP : X86::ESP; in populateThunk() local
236 addRegOffset(BuildMI(CallTarget, DebugLoc(), TII->get(MovOpc)), SPReg, false, in populateThunk()
H A DX86FrameLowering.h115 Register &SPReg) const;
117 Register &SPReg, int Adjustment) const;
H A DX86CallLowering.cpp
H A DX86FrameLowering.cpp2297 Register SPReg; in getPSPSlotOffsetFromSP() local
2298 int Offset = getFrameIndexReferencePreferSP(MF, Info.PSPSymFrameIdx, SPReg, in getPSPSlotOffsetFromSP()
2301 assert(Offset >= 0 && SPReg == TRI->getStackRegister()); in getPSPSlotOffsetFromSP()
3600 unsigned ScratchReg, SPReg, PReg, SPLimitOffset; in adjustForHiPEPrologue() local
3604 SPReg = X86::RSP; in adjustForHiPEPrologue()
3610 SPReg = X86::ESP; in adjustForHiPEPrologue()
3622 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg), SPReg, in adjustForHiPEPrologue()
3633 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg), SPReg, in adjustForHiPEPrologue()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp77 if (!SPReg) in getStackAddress()
78 SPReg = MIRBuilder.buildCopy(p0, Register(RISCV::X2)).getReg(0); in getStackAddress()
82 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
168 Register SPReg; member
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp83 auto SPReg = MIRBuilder.buildCopy(p0, StackReg).getReg(0); in getStackAddress() local
85 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp704 unsigned SPReg = Xtensa::SP; in LowerDYNAMIC_STACKALLOC() local
705 SDValue SP = DAG.getCopyFromReg(Chain, DL, SPReg, VT); in LowerDYNAMIC_STACKALLOC()
707 Chain = DAG.getCopyToReg(SP.getValue(1), DL, SPReg, NewSP); // Output chain in LowerDYNAMIC_STACKALLOC()
709 SDValue NewVal = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32); in LowerDYNAMIC_STACKALLOC()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp98 auto SPReg = in getStackAddress() local
103 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp109 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP)); in getStackAddress() local
113 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp184 Register SPReg; member
211 if (!SPReg) { in getStackAddress()
215 SPReg = MIRBuilder.buildCopy(PtrTy, in getStackAddress()
221 SPReg = MIRBuilder.buildInstr(AMDGPU::G_AMDGPU_WAVE_ADDRESS, {PtrTy}, in getStackAddress()
228 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress()
H A DSIFrameLowering.cpp700 Register SPReg = MFI->getStackPtrOffsetReg(); in emitEntryFunctionPrologue() local
701 assert(SPReg != AMDGPU::SP_REG); in emitEntryFunctionPrologue()
702 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), SPReg) in emitEntryFunctionPrologue()
1784 Register SPReg = MFI->getStackPtrOffsetReg(); in eliminateCallFramePseudoInstr() local
1789 auto Add = BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), SPReg) in eliminateCallFramePseudoInstr()
1790 .addReg(SPReg) in eliminateCallFramePseudoInstr()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp270 if (!SPReg) in getStackAddress()
271 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0); in getStackAddress()
275 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
346 Register SPReg; member
H A DAArch64LegalizerInfo.cpp2176 Register SPReg = in legalizeDynStackAlloc() local
2179 Helper.getDynStackAllocTargetPtr(SPReg, AllocSize, Alignment, PtrTy); in legalizeDynStackAlloc()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp237 auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP)); in getStackAddress()
240 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
236 auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP)); getStackAddress() local
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp1333 unsigned SPReg = Regs.getStackPointerRegister(); in emitEpilogue() local
1334 if (ZFI->getRestoreGPRRegs().LowGPR != SPReg) { in emitEpilogue()
1336 emitIncrement(MBB, MBBI, DL, SPReg, StackSize, ZII); in emitEpilogue()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizerHelper.h417 Register getDynStackAllocTargetPtr(Register SPReg, Register AllocSize,
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp1024 Register SPReg = getStackPointerRegisterToSaveRestore(); in LowerDYNAMIC_STACKALLOC() local
1027 SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32); in LowerDYNAMIC_STACKALLOC()
1047 SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub); in LowerDYNAMIC_STACKALLOC()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp3409 Register SPReg = TLI.getStackPointerRegisterToSaveRestore(); in LowerDYNAMIC_STACKALLOC() local
3410 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" in LowerDYNAMIC_STACKALLOC()
3413 SDValue SP = DAG.getCopyFromReg(Chain, DL, SPReg, VT); in LowerDYNAMIC_STACKALLOC()
3421 Chain = DAG.getCopyToReg(Chain, DL, SPReg, Result); // Output chain in LowerDYNAMIC_STACKALLOC()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp12088 int SPReg = tryParseRegister(); in parseDirectiveSetFP() local
12089 if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") || in parseDirectiveSetFP()
12090 check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc, in parseDirectiveSetFP()
12120 static_cast<unsigned>(SPReg), Offset); in parseDirectiveSetFP()
12407 int SPReg = tryParseRegister(); in parseDirectiveMovSP() local
12408 if (SPReg == -1) in parseDirectiveMovSP()
12410 if (SPReg == ARM::SP || SPReg == ARM::PC) in parseDirectiveMovSP()
12434 getTargetStreamer().emitMovSP(SPReg, Offset); in parseDirectiveMovSP()
12435 UC.saveFPReg(SPReg); in parseDirectiveMovSP()

12