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Searched refs:SOffset (Results 1 – 18 of 18) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.h131 bool isSOffsetLegalWithImmOffset(SDValue *SOffset, bool Imm32Only,
142 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
145 SDValue &SOffset, SDValue &Offset) const;
147 SDValue &VAddr, SDValue &SOffset,
154 bool SelectBUFSOffset(SDValue Addr, SDValue &SOffset) const;
173 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue *SOffset,
178 bool SelectSMRDBaseOffset(SDValue Addr, SDValue &SBase, SDValue *SOffset,
182 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue *SOffset,
186 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &SOffset) const;
187 bool SelectSMRDSgprImm(SDValue Addr, SDValue &SBase, SDValue &SOffset,
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H A DAMDGPUISelDAGToDAG.cpp1454 SDValue &SOffset, SDValue &Offset, in SelectMUBUF() argument
1467 SOffset = Subtarget->hasRestrictedSOffset() in SelectMUBUF()
1533 SOffset = in SelectMUBUF()
1542 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFAddr64() argument
1551 if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64)) in SelectMUBUFAddr64()
1584 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFScratchOffen() argument
1606 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectMUBUFScratchOffen()
1637 std::tie(VAddr, SOffset) = foldFrameIndex(N0); in SelectMUBUFScratchOffen()
1644 std::tie(VAddr, SOffset) = foldFrameIndex(Addr); in SelectMUBUFScratchOffen()
1662 SDValue &SOffset, in SelectMUBUFScratchOffset() argument
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H A DAMDGPUInstructionSelector.h229 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
303 Register &SOffset, int64_t &ImmOffset) const;
308 Register &RSrcReg, Register &SOffset,
312 Register &SOffset, int64_t &Offset) const;
H A DSIRegisterInfo.cpp1128 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex() local
1129 assert(SOffset->isImm() && SOffset->getImm() == 0); in resolveFrameIndex()
1588 MCRegister SOffset = ScratchOffsetReg; in buildSpillLoadStore() local
1662 if (!IsOffsetLegal || (IsFlat && !SOffset && !ST.hasFlatScratchSTMode())) { in buildSpillLoadStore()
1663 SOffset = MCRegister(); in buildSpillLoadStore()
1670 SOffset = RS->scavengeRegisterBackwards(AMDGPU::SGPR_32RegClass, MI, false, 0, false); in buildSpillLoadStore()
1678 SOffset = Reg; in buildSpillLoadStore()
1685 SOffset = Register(); in buildSpillLoadStore()
1687 if (!SOffset) { in buildSpillLoadStore()
1703 } else if (!SOffset && CanClobberSCC) { in buildSpillLoadStore()
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H A DAMDGPUInstructionSelector.cpp5204 Register *SOffset, in selectSmrdOffset() argument
5220 if (SOffset && Offset) { in selectSmrdOffset()
5230 *SOffset = OffsetReg; in selectSmrdOffset()
5239 auto SKnown = VT->getKnownBits(*SOffset); in selectSmrdOffset()
5259 if (SOffset && GEPI.SgprParts.size() == 1 && isUInt<32>(GEPI.Imm) && in selectSmrdOffset()
5266 *SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectSmrdOffset()
5267 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), *SOffset) in selectSmrdOffset()
5272 if (SOffset && GEPI.SgprParts.size() && GEPI.Imm == 0) { in selectSmrdOffset()
5275 *SOffset = OffsetReg; in selectSmrdOffset()
5317 Register Base, SOffset; in selectSmrdSgpr() local
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H A DSILoadStoreOptimizer.cpp98 bool SOffset = false; member
693 Result.SOffset = true; in getRegs()
721 Result.SOffset = true; in getRegs()
738 Result.SOffset = true; in getRegs()
869 if (Regs.SOffset) in setMI()
H A DAMDGPURegisterBankInfo.cpp1264 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1265 if (TII->splitMUBUFOffset(*Imm, SOffset, ImmOffset, Alignment)) { in setBufferOffsets()
1267 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1272 return SOffset + ImmOffset; in setBufferOffsets()
1282 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1284 TII->splitMUBUFOffset(Offset, SOffset, ImmOffset, Alignment)) { in setBufferOffsets()
1287 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1294 if (SOffset == 0) { in setBufferOffsets()
1390 Register SOffset; in applyMappingSBufferLoad() local
1395 SOffset, ImmOffset, Alignment); in applyMappingSBufferLoad()
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H A DSIISelLowering.cpp9361 static SDValue selectSOffset(SDValue SOffset, SelectionDAG &DAG, in selectSOffset() argument
9363 if (Subtarget->hasRestrictedSOffset() && isNullConstant(SOffset)) in selectSOffset()
9365 return SOffset; in selectSOffset()
9376 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); in lowerRawBufferAtomicIntrin() local
9383 SOffset, // soffset in lowerRawBufferAtomicIntrin()
9404 auto SOffset = selectSOffset(Op.getOperand(6), DAG, Subtarget); in lowerStructBufferAtomicIntrin() local
9411 SOffset, // soffset in lowerStructBufferAtomicIntrin()
9505 auto SOffset = selectSOffset(Op.getOperand(4), DAG, Subtarget); in LowerINTRINSIC_W_CHAIN() local
9511 SOffset, // soffset in LowerINTRINSIC_W_CHAIN()
9532 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); in LowerINTRINSIC_W_CHAIN() local
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H A DAMDGPULegalizerInfo.cpp5954 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferStore() local
5992 .addUse(SOffset) // soffset in legalizeBufferStore()
6007 Register VIndex, Register VOffset, Register SOffset, in buildBufferLoad() argument
6016 .addUse(SOffset) // soffset in buildBufferLoad()
6068 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferLoad() local
6143 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
6163 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
6170 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
6180 buildBufferLoad(Opc, Dst, RSrc, VIndex, VOffset, SOffset, ImmOffset, Format, in legalizeBufferLoad()
6315 Register SOffset = MI.getOperand(5 + OpOffset).getReg(); in legalizeBufferAtomic() local
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H A DGCNHazardRecognizer.cpp815 const MachineOperand *SOffset = in createsVALUHazard() local
820 (!SOffset || !SOffset->isReg())) in createsVALUHazard()
H A DBUFInstructions.td168 dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset),
171 dag NonVaddrInputs = !con((ins SReg_128_XNULL:$srsrc), SOffset,
420 dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
421 …dag NonVaddrInputs = !con((ins SReg_128_XNULL:$srsrc), SOffset, (ins Offset:$offset, CPol_0:$cpol,…
686 dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
687 dag MainInputs = !con((ins SReg_128_XNULL:$srsrc), SOffset, (ins Offset:$offset));
H A DSIInstrInfo.cpp451 const MachineOperand *SOffset = in getMemOperandsWithOffsetWidth() local
453 if (SOffset) { in getMemOperandsWithOffsetWidth()
454 if (SOffset->isReg()) in getMemOperandsWithOffsetWidth()
455 BaseOps.push_back(SOffset); in getMemOperandsWithOffsetWidth()
457 Offset += SOffset->getImm(); in getMemOperandsWithOffsetWidth()
7183 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); in legalizeOperands() local
7198 .add(*SOffset) in legalizeOperands()
7222 .add(*SOffset) in legalizeOperands()
9478 bool SIInstrInfo::splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, in splitMUBUFOffset() argument
9519 SOffset = Overflow; in splitMUBUFOffset()
H A DAMDGPULowerBufferFatPointers.cpp2295 Value *SOffset = IRB.getInt32(0); in visitIntrinsicInst() local
2298 {Rsrc, LDSPtr, LoadSize, Off, SOffset, ImmOff, Aux}); in visitIntrinsicInst()
H A DSIInstrInfo.h1447 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
H A DAMDGPU.td1094 "Has restricted SOffset (immediate not supported)."
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp749 unsigned SOffset = 0; in getMachineOpValue() local
766 ++SOffset; in getMachineOpValue()
792 : SOffset; in getMachineOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp315 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall() local
317 ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), StackPtr, SOffset); in LowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp6328 StackOffset &SOffset, in isAArch64FrameOffsetLegal() argument
6386 int64_t Offset = IsMulVL ? SOffset.getScalable() : SOffset.getFixed(); in isAArch64FrameOffsetLegal()
6428 SOffset = StackOffset::get(SOffset.getFixed(), Offset); in isAArch64FrameOffsetLegal()
6430 SOffset = StackOffset::get(Offset, SOffset.getScalable()); in isAArch64FrameOffsetLegal()
6432 (SOffset ? 0 : AArch64FrameOffsetIsLegal); in isAArch64FrameOffsetLegal()