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Searched refs:SOffset (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.h135 bool isSOffsetLegalWithImmOffset(SDValue *SOffset, bool Imm32Only,
146 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
149 SDValue &SOffset, SDValue &Offset) const;
151 SDValue &VAddr, SDValue &SOffset,
158 bool SelectBUFSOffset(SDValue Addr, SDValue &SOffset) const;
177 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue *SOffset,
182 bool SelectSMRDBaseOffset(SDValue Addr, SDValue &SBase, SDValue *SOffset,
186 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue *SOffset,
190 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &SOffset) const;
191 bool SelectSMRDSgprImm(SDValue Addr, SDValue &SBase, SDValue &SOffset,
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H A DAMDGPUISelDAGToDAG.cpp1339 SDValue &SOffset, SDValue &Offset, in SelectMUBUF() argument
1352 SOffset = Subtarget->hasRestrictedSOffset() in SelectMUBUF()
1418 SOffset = in SelectMUBUF()
1427 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFAddr64() argument
1436 if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64)) in SelectMUBUFAddr64()
1469 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFScratchOffen() argument
1491 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectMUBUFScratchOffen()
1522 std::tie(VAddr, SOffset) = foldFrameIndex(N0); in SelectMUBUFScratchOffen()
1529 std::tie(VAddr, SOffset) = foldFrameIndex(Addr); in SelectMUBUFScratchOffen()
1547 SDValue &SOffset, in SelectMUBUFScratchOffset() argument
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H A DAMDGPUInstructionSelector.h221 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
295 Register &SOffset, int64_t &ImmOffset) const;
300 Register &RSrcReg, Register &SOffset,
304 Register &SOffset, int64_t &Offset) const;
H A DSIRegisterInfo.cpp915 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex() local
916 assert(SOffset->isImm() && SOffset->getImm() == 0); in resolveFrameIndex()
1347 MCRegister SOffset = ScratchOffsetReg; in buildSpillLoadStore() local
1418 if (!IsOffsetLegal || (IsFlat && !SOffset && !ST.hasFlatScratchSTMode())) { in buildSpillLoadStore()
1419 SOffset = MCRegister(); in buildSpillLoadStore()
1426 SOffset = RS->scavengeRegisterBackwards(AMDGPU::SGPR_32RegClass, MI, false, 0, false); in buildSpillLoadStore()
1434 SOffset = Reg; in buildSpillLoadStore()
1441 SOffset = Register(); in buildSpillLoadStore()
1443 if (!SOffset) { in buildSpillLoadStore()
1459 } else if (!SOffset && CanClobberSCC) { in buildSpillLoadStore()
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H A DAMDGPUInstructionSelector.cpp4170 Register *SOffset, in selectSmrdOffset() argument
4186 if (SOffset && Offset) { in selectSmrdOffset()
4196 *SOffset = OffsetReg; in selectSmrdOffset()
4205 auto SKnown = KB->getKnownBits(*SOffset); in selectSmrdOffset()
4225 if (SOffset && GEPI.SgprParts.size() == 1 && isUInt<32>(GEPI.Imm) && in selectSmrdOffset()
4232 *SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectSmrdOffset()
4233 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), *SOffset) in selectSmrdOffset()
4238 if (SOffset && GEPI.SgprParts.size() && GEPI.Imm == 0) { in selectSmrdOffset()
4241 *SOffset = OffsetReg; in selectSmrdOffset()
4283 Register Base, SOffset; in selectSmrdSgpr() local
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H A DSILoadStoreOptimizer.cpp97 bool SOffset = false; member
665 Result.SOffset = true; in getRegs()
693 Result.SOffset = true; in getRegs()
706 Result.SOffset = true; in getRegs()
833 if (Regs.SOffset) in setMI()
H A DAMDGPURegisterBankInfo.cpp1254 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1255 if (TII->splitMUBUFOffset(*Imm, SOffset, ImmOffset, Alignment)) { in setBufferOffsets()
1257 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1262 return SOffset + ImmOffset; in setBufferOffsets()
1272 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1274 TII->splitMUBUFOffset(Offset, SOffset, ImmOffset, Alignment)) { in setBufferOffsets()
1277 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1284 if (SOffset == 0) { in setBufferOffsets()
1362 Register SOffset; in applyMappingSBufferLoad() local
1367 SOffset, ImmOffset, Alignment); in applyMappingSBufferLoad()
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H A DSIISelLowering.cpp8775 static SDValue selectSOffset(SDValue SOffset, SelectionDAG &DAG, in selectSOffset() argument
8777 if (Subtarget->hasRestrictedSOffset() && isNullConstant(SOffset)) in selectSOffset()
8779 return SOffset; in selectSOffset()
8790 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); in lowerRawBufferAtomicIntrin() local
8797 SOffset, // soffset in lowerRawBufferAtomicIntrin()
8818 auto SOffset = selectSOffset(Op.getOperand(6), DAG, Subtarget); in lowerStructBufferAtomicIntrin() local
8825 SOffset, // soffset in lowerStructBufferAtomicIntrin()
8910 auto SOffset = selectSOffset(Op.getOperand(4), DAG, Subtarget); in LowerINTRINSIC_W_CHAIN() local
8916 SOffset, // soffset in LowerINTRINSIC_W_CHAIN()
8935 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); in LowerINTRINSIC_W_CHAIN() local
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H A DAMDGPULegalizerInfo.cpp5839 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferStore() local
5877 .addUse(SOffset) // soffset in legalizeBufferStore()
5892 Register VIndex, Register VOffset, Register SOffset, in buildBufferLoad() argument
5901 .addUse(SOffset) // soffset in buildBufferLoad()
5950 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferLoad() local
6013 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
6033 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
6040 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
6050 buildBufferLoad(Opc, Dst, RSrc, VIndex, VOffset, SOffset, ImmOffset, Format, in legalizeBufferLoad()
6185 Register SOffset = MI.getOperand(5 + OpOffset).getReg(); in legalizeBufferAtomic() local
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H A DGCNHazardRecognizer.cpp832 const MachineOperand *SOffset = in createsVALUHazard() local
837 (!SOffset || !SOffset->isReg())) in createsVALUHazard()
H A DBUFInstructions.td165 dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset),
168 dag NonVaddrInputs = !con((ins SReg_128:$srsrc), SOffset,
416 dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
417 …dag NonVaddrInputs = !con((ins SReg_128:$srsrc), SOffset, (ins Offset:$offset, CPol_0:$cpol, i1imm…
693 dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
694 dag MainInputs = !con((ins SReg_128:$srsrc), SOffset, (ins Offset:$offset));
H A DSIInstrInfo.cpp441 const MachineOperand *SOffset = in getMemOperandsWithOffsetWidth() local
443 if (SOffset) { in getMemOperandsWithOffsetWidth()
444 if (SOffset->isReg()) in getMemOperandsWithOffsetWidth()
445 BaseOps.push_back(SOffset); in getMemOperandsWithOffsetWidth()
447 Offset += SOffset->getImm(); in getMemOperandsWithOffsetWidth()
6861 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); in legalizeOperands() local
6876 .add(*SOffset) in legalizeOperands()
6900 .add(*SOffset) in legalizeOperands()
9047 bool SIInstrInfo::splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, in splitMUBUFOffset() argument
9088 SOffset = Overflow; in splitMUBUFOffset()
H A DSIInstrInfo.h1382 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
H A DAMDGPU.td947 "Has restricted SOffset (immediate not supported)."
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp722 unsigned SOffset = 0; in getMachineOpValue() local
739 ++SOffset; in getMachineOpValue()
765 : SOffset; in getMachineOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp332 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall() local
334 ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), StackPtr, SOffset); in LowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp5659 StackOffset &SOffset, in isAArch64FrameOffsetLegal() argument
5717 int64_t Offset = IsMulVL ? SOffset.getScalable() : SOffset.getFixed(); in isAArch64FrameOffsetLegal()
5759 SOffset = StackOffset::get(SOffset.getFixed(), Offset); in isAArch64FrameOffsetLegal()
5761 SOffset = StackOffset::get(Offset, SOffset.getScalable()); in isAArch64FrameOffsetLegal()
5763 (SOffset ? 0 : AArch64FrameOffsetIsLegal); in isAArch64FrameOffsetLegal()