4170                                                  Register *SOffset,  in selectSmrdOffset()  argument
4186   if (SOffset && Offset) {  in selectSmrdOffset()
4196           *SOffset = OffsetReg;  in selectSmrdOffset()
4205           auto SKnown = KB->getKnownBits(*SOffset);  in selectSmrdOffset()
4225   if (SOffset && GEPI.SgprParts.size() == 1 && isUInt<32>(GEPI.Imm) &&  in selectSmrdOffset()
4232     *SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectSmrdOffset()
4233     BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), *SOffset)  in selectSmrdOffset()
4238   if (SOffset && GEPI.SgprParts.size() && GEPI.Imm == 0) {  in selectSmrdOffset()
4241       *SOffset = OffsetReg;  in selectSmrdOffset()
4283   Register Base, SOffset;  in selectSmrdSgpr()  local
4284   if (!selectSmrdOffset(Root, Base, &SOffset, /* Offset= */ nullptr))  in selectSmrdSgpr()
4288            [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}};  in selectSmrdSgpr()
4293   Register Base, SOffset;  in selectSmrdSgprImm()  local
4295   if (!selectSmrdOffset(Root, Base, &SOffset, &Offset))  in selectSmrdSgprImm()
4299            [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },  in selectSmrdSgprImm()
5112   MachineIRBuilder &B, Register &SOffset, int64_t &ImmOffset) const {  in splitIllegalMUBUFOffset()  argument
5117   SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in splitIllegalMUBUFOffset()
5119     .addDef(SOffset)  in splitIllegalMUBUFOffset()
5126   Register &SOffset, int64_t &Offset) const {  in selectMUBUFAddr64Impl()  argument
5171   splitIllegalMUBUFOffset(B, SOffset, Offset);  in selectMUBUFAddr64Impl()
5176   MachineOperand &Root, Register &RSrcReg, Register &SOffset,  in selectMUBUFOffsetImpl()  argument
5196   splitIllegalMUBUFOffset(B, SOffset, Offset);  in selectMUBUFOffsetImpl()
5204   Register SOffset;  in selectMUBUFAddr64()  local
5207   if (!selectMUBUFAddr64Impl(Root, VAddr, RSrcReg, SOffset, Offset))  in selectMUBUFAddr64()
5220         if (SOffset)  in selectMUBUFAddr64()
5221           MIB.addReg(SOffset);  in selectMUBUFAddr64()
5239   Register SOffset;  in selectMUBUFOffset()  local
5242   if (!selectMUBUFOffsetImpl(Root, RSrcReg, SOffset, Offset))  in selectMUBUFOffset()
5250         if (SOffset)  in selectMUBUFOffset()
5251           MIB.addReg(SOffset);  in selectMUBUFOffset()
5267   Register SOffset = Root.getReg();  in selectBUFSOffset()  local
5269   if (STI.hasRestrictedSOffset() && mi_match(SOffset, *MRI, m_ZeroInt()))  in selectBUFSOffset()
5270     SOffset = AMDGPU::SGPR_NULL;  in selectBUFSOffset()
5272   return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}};  in selectBUFSOffset()
5319   Register SOffset;  in selectSMRDBufferSgprImm()  local
5321   std::tie(SOffset, Offset) = AMDGPU::getBaseWithConstantOffset(  in selectSMRDBufferSgprImm()
5323   if (!SOffset)  in selectSMRDBufferSgprImm()
5331   assert(MRI->getType(SOffset) == LLT::scalar(32));  in selectSMRDBufferSgprImm()
5332   return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },  in selectSMRDBufferSgprImm()