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Searched refs:SMULL (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h329 SMULL, enumerator
H A DAArch64ISelLowering.cpp2751 MAKE_CASE(AArch64ISD::SMULL) in getTargetNodeName()
5220 return AArch64ISD::SMULL; in selectUmullSmull()
5244 return AArch64ISD::SMULL; in selectUmullSmull()
5264 return AArch64ISD::SMULL; in selectUmullSmull()
7169 N1.getOpcode() == AArch64ISD::SMULL) in isReassocProfitable()
20405 if (M1.getOpcode() != ISD::MUL && M1.getOpcode() != AArch64ISD::SMULL && in performSubAddMULCombine()
20408 if (M2.getOpcode() != ISD::MUL && M2.getOpcode() != AArch64ISD::SMULL && in performSubAddMULCombine()
21274 return DAG.getNode(AArch64ISD::SMULL, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
25409 case AArch64ISD::SMULL: in PerformDAGCombine()
H A DAArch64InstrInfo.td844 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull,
6312 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", AArch64smull>;
7815 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull", AArch64smull>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleR52.td278 "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$",
H A DARMScheduleSwift.td281 (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>;
H A DARMScheduleA57.td290 // Multiply long: SMULL, UMULL
H A DARMInstrInfo.td4384 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4406 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
6437 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6454 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
H A DARMScheduleA9.td2551 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp8500 case ARM::SMULL: in validateInstruction()