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Searched refs:SETCC (Results 1 – 25 of 64) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3252 { ISD::SETCC, MVT::v2i64, { 2, 5, 1, 2 } }, in getCmpSelInstrCost()
3263 { ISD::SETCC, MVT::v32i16, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3264 { ISD::SETCC, MVT::v16i16, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3265 { ISD::SETCC, MVT::v64i8, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3266 { ISD::SETCC, MVT::v32i8, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3273 { ISD::SETCC, MVT::v8f64, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3274 { ISD::SETCC, MVT::v4f64, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3275 { ISD::SETCC, MVT::v16f32, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3276 { ISD::SETCC, MVT::v8f32, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3278 { ISD::SETCC, MVT::v8i64, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.h185 static inline bool IsSETCC(unsigned SETCC) { in IsSETCC() argument
186 switch (SETCC) { in IsSETCC()
H A DM68kISelLowering.cpp129 setOperationAction(ISD::SETCC, VT, Custom); in M68kTargetLowering()
1389 case ISD::SETCC: in LowerOperation()
1644 Overflow = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1), in LowerXALUO()
1670 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in getBitTestCondition()
1860 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC && in hasNonFlagsUse()
2172 if (Op0.getOpcode() == M68kISD::SETCC) { in LowerSETCC()
2180 DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCC()
2204 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCC()
2228 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCCCARRY()
2268 if (Cond.getOpcode() == ISD::SETCC) { in LowerSELECT()
[all …]
H A DM68kISelLowering.h53 SETCC, enumerator
55 // Same as SETCC except it's materialized with a subx and the value is all
129 /// Return the value type to use for ISD::SETCC.
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h40 // SETCC - Store the conditional code to a register.
41 SETCC, enumerator
H A DLanaiISelLowering.cpp88 setOperationAction(ISD::SETCC, MVT::i32, Custom); in LanaiTargetLowering()
190 case ISD::SETCC: in LowerOperation()
981 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Glue); in LowerSETCC()
1105 case LanaiISD::SETCC: in getTargetNodeName()
1495 case LanaiISD::SETCC: in computeKnownBitsForTargetNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h54 SETCC, enumerator
H A DMSP430ISelLowering.cpp92 setOperationAction(ISD::SETCC, MVT::i8, Custom); in MSP430TargetLowering()
93 setOperationAction(ISD::SETCC, MVT::i16, Custom); in MSP430TargetLowering()
348 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
1379 case MSP430ISD::SETCC: return "MSP430ISD::SETCC"; in getTargetNodeName()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def119 ADD_VVP_OP(VVP_SETCC, SETCC)
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def65 // Both of these match to FCmp / SETCC.
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h778 SETCC, enumerator
H A DSDPatternMatch.h482 return TernaryOpc_match<T0_P, T1_P, T2_P, false, false>(ISD::SETCC, LHS, RHS,
489 return TernaryOpc_match<T0_P, T1_P, T2_P, true, false>(ISD::SETCC, LHS, RHS,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp503 case ISD::SETCC: { in LegalizeOp()
683 case ISD::SETCC: in Promote()
896 DAG.getNode(ISD::SETCC, SDLoc(Node), CondVT, Node->getOperand(0), in Expand()
917 case ISD::SETCC: in Expand()
1743 LHS = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), LHS, RHS, CC, in ExpandSETCC()
2025 Ops[i] = DAG.getNode(ISD::SETCC, dl, in UnrollVSETCC()
H A DLegalizeVectorTypes.cpp73 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; in ScalarizeVectorResult()
587 if (Cond->getOpcode() == ISD::SETCC) { in ScalarizeVecRes_VSELECT()
694 // Turn it into a scalar SETCC. in ScalarizeVecRes_SETCC()
695 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecRes_SETCC()
776 case ISD::SETCC: in ScalarizeVectorOperand()
911 /// result must be v1i1, so just convert to a scalar SETCC and wrap in ScalarizeVecOp_VSETCC()
926 // Turn it into a scalar SETCC. in ScalarizeVecOp_VSETCC()
927 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecOp_VSETCC()
1120 case ISD::SETCC: in SplitVectorResult()
2098 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_VP_LOAD()
[all...]
H A DDAGCombiner.cpp969 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
1271 if (N1->getOpcode() == ISD::SETCC && N00->getOpcode() == ISD::SETCC && in reassociateOpsCommutative()
1272 N01->getOpcode() == ISD::SETCC) { in reassociateOpsCommutative()
1905 case ISD::SETCC: return visitSETCC(N); in visit()
5578 if (N0.getOperand(0).getOpcode() != ISD::SETCC) in isSaturatingMinMax()
6078 TLI.isOperationLegal(ISD::SETCC, OpVT)))) in foldLogicOfSetCCs()
6160 if (LHS->getOpcode() != ISD::SETCC || RHS->getOpcode() != ISD::SETCC || in foldAndOrOfSETCC()
6287 return DAG.getNode(ISD::SETCC, DL, VT, AbsOp, in foldAndOrOfSETCC()
6317 return DAG.getNode(ISD::SETCC, DL, VT, AndOp, in foldAndOrOfSETCC()
6325 return DAG.getNode(ISD::SETCC, DL, VT, AndOp, in foldAndOrOfSETCC()
[all …]
H A DLegalizeDAG.cpp1040 case ISD::SETCC: in LegalizeOp()
1049 : (Opc == ISD::SETCC || Opc == ISD::VP_SETCC) ? 2 in LegalizeOp()
4013 if (Tmp1.getOpcode() == ISD::SETCC) { in ExpandNode()
4073 if (Tmp2.getOpcode() == ISD::SETCC && in ExpandNode()
4094 case ISD::SETCC: in ExpandNode()
4185 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC, Node->getFlags()); in ExpandNode()
5089 Node->getOpcode() == ISD::SETCC || in PromoteNode()
5382 case ISD::SETCC: in PromoteNode()
5411 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), Tmp1, in PromoteNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp169 setOperationAction(ISD::SETCC, P, Custom); in initializeHVXLowering()
305 setOperationAction(ISD::SETCC, T, Custom); in initializeHVXLowering()
376 setOperationAction(ISD::SETCC, BoolW, Custom); in initializeHVXLowering()
420 setOperationAction(ISD::SETCC, VecTy, Custom); in initializeHVXLowering()
434 setOperationAction(ISD::SETCC, BoolTy, Custom); in initializeHVXLowering()
3129 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy, in WidenHvxSetCC()
3185 case ISD::SETCC: in LowerHvxOperation()
3226 case ISD::SETCC: in LowerHvxOperation()
3376 case ISD::SETCC: in LowerHvxOperationWrapper()
3442 case ISD::SETCC in ReplaceHvxNodeResults()
[all...]
H A DHexagonISelLowering.cpp1535 setOperationAction(ISD::SETCC, MVT::i8, Custom); in HexagonTargetLowering()
1536 setOperationAction(ISD::SETCC, MVT::i16, Custom); in HexagonTargetLowering()
1537 setOperationAction(ISD::SETCC, MVT::v4i8, Custom); in HexagonTargetLowering()
1538 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1776 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
3395 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp102 {ISD::SHL, ISD::SRA, ISD::SRL, ISD::SETCC, ISD::VSELECT}); in MipsSETargetLowering()
124 setOperationAction(ISD::SETCC, MVT::f16, Promote); in MipsSETargetLowering()
244 setOperationAction(ISD::SETCC, MVT::i32, Legal); in MipsSETargetLowering()
248 setOperationAction(ISD::SETCC, MVT::f32, Legal); in MipsSETargetLowering()
253 setOperationAction(ISD::SETCC, MVT::f64, Legal); in MipsSETargetLowering()
291 setOperationAction(ISD::SETCC, MVT::i64, Legal); in MipsSETargetLowering()
359 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAIntType()
396 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAFloatType()
1050 case ISD::SETCC: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp113 setOperationAction(ISD::SETCC, MVT::i8, Custom); in AVRTargetLowering()
114 setOperationAction(ISD::SETCC, MVT::i16, Custom); in AVRTargetLowering()
115 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AVRTargetLowering()
116 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AVRTargetLowering()
996 case ISD::SETCC: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp97 setOperationAction(ISD::SETCC, {MVT::v4i32, MVT::v2i32}, Expand); in R600TargetLowering()
109 setOperationAction(ISD::SETCC, {MVT::i32, MVT::f32}, Expand); in R600TargetLowering()
745 ISD::SETCC, in lowerFP_TO_UINT()
755 ISD::SETCC, in lowerFP_TO_SINT()
H A DAMDGPUISelLowering.h446 SETCC, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp448 case ISD::SETCC: in NVPTXTargetLowering()
502 setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote); in NVPTXTargetLowering()
503 setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand); in NVPTXTargetLowering()
511 setBF16OperationAction(ISD::SETCC, MVT::v2bf16, Legal, Expand); in NVPTXTargetLowering()
512 setBF16OperationAction(ISD::SETCC, MVT::bf16, Legal, Promote); in NVPTXTargetLowering()
513 if (getOperationAction(ISD::SETCC, MVT::bf16) == Promote) in NVPTXTargetLowering()
514 AddPromotedToType(ISD::SETCC, MVT::bf16, MVT::f32); in NVPTXTargetLowering()
535 ISD::SETCC, ISD::SHL, ISD::SINT_TO_FP, ISD::SMAX, in NVPTXTargetLowering()
738 setTargetDAGCombine(ISD::SETCC); in NVPTXTargetLowering()
6030 case ISD::SETCC: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp478 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AArch64TargetLowering()
479 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AArch64TargetLowering()
480 setOperationAction(ISD::SETCC, MVT::bf16, Custom); in AArch64TargetLowering()
481 setOperationAction(ISD::SETCC, MVT::f16, Custom); in AArch64TargetLowering()
482 setOperationAction(ISD::SETCC, MVT::f32, Custom); in AArch64TargetLowering()
483 setOperationAction(ISD::SETCC, MVT::f64, Custom); in AArch64TargetLowering()
552 setOperationAction(ISD::SETCC, MVT::f128, Custom); in AArch64TargetLowering()
757 ISD::SETCC, in AArch64TargetLowering()
824 setOperationAction(ISD::SETCC, V4Narrow, Custom); in AArch64TargetLowering()
848 setOperationAction(ISD::SETCC, V8Narrow, Expand); in AArch64TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp263 setOperationAction(ISD::SETCC, MVT::i32, Promote); in RISCVTargetLowering()
460 ISD::SETCC, ISD::FCEIL, ISD::FFLOOR, in RISCVTargetLowering()
951 ISD::FNEARBYINT, ISD::IS_FPCLASS, ISD::SETCC, ISD::FMAXIMUM, in RISCVTargetLowering()
1167 setOperationAction(ISD::SETCC, VT, Custom); in RISCVTargetLowering()
1380 setOperationAction(ISD::SETCC, VT, Custom); in RISCVTargetLowering()
1472 ISD::AND, ISD::OR, ISD::XOR, ISD::SETCC, ISD::SELECT}); in RISCVTargetLowering()
4032 // A BUILD_VECTOR can be lowered as a SETCC. For each fixed-length mask in lowerBUILD_VECTOR()
6018 VP_CASE(SETCC) // VP_SETCC in getRISCVVLOp()
6929 // into separate SETCC+SELECT just like LegalizeDAG. in LowerOperation()
6941 DAG.getNode(ISD::SETCC, D in LowerOperation()
[all...]

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