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Searched refs:SDep (Results 1 – 25 of 42) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUExportClustering.cpp68 for (const SDep &Pred : SUb->Preds) { in buildCluster()
71 DAG->addEdge(ChainHead, SDep(PredSU, SDep::Artificial)); in buildCluster()
75 DAG->addEdge(SUb, SDep(SUa, SDep::Barrier)); in buildCluster()
77 DAG->addEdge(SUb, SDep(SUa, SDep::Cluster)); in buildCluster()
82 SmallVector<SDep, 2> ToAdd, ToRemove; in removeExportDependencies()
84 for (const SDep &Pred : SU.Preds) { in removeExportDependencies()
93 for (const SDep &ExportPred : PredSU->Preds) { in removeExportDependencies()
96 ToAdd.push_back(SDep(ExportPredSU, SDep::Barrier)); in removeExportDependencies()
101 for (SDep Pred : ToRemove) in removeExportDependencies()
103 for (SDep Pred : ToAdd) in removeExportDependencies()
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H A DSIMachineScheduler.cpp418 for (SDep& Succ : SU->Succs) { in undoSchedule()
428 void SIScheduleBlock::undoReleaseSucc(SUnit *SU, SDep *SuccEdge) { in undoReleaseSucc()
438 void SIScheduleBlock::releaseSucc(SUnit *SU, SDep *SuccEdge) { in releaseSucc()
459 for (SDep& Succ : SU->Succs) { in releaseSuccessors()
491 for (SDep& Succ : SU->Succs) { in nodeScheduled()
641 PredDep.getKind() == llvm::SDep::Data) in hasDataDependencyPred()
791 for (SDep& PredDep : SU->Preds) { in colorComputeReservedDependencies()
829 for (SDep& SuccDep : SU->Succs) { in colorComputeReservedDependencies()
906 for (SDep& SuccDep : SU->Succs) { in colorEndsAccordingToDependencies()
976 for (SDep& SuccDep : SU->Succs) { in colorMergeConstantLoadsNextGroup()
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H A DGCNMinRegStrategy.cpp88 for (auto SDep : SU->Succs) { in getReadySuccessors() local
90 for (auto PDep : SDep.getSUnit()->Preds) { in getReadySuccessors()
181 S.getKind() != SDep::Data) in bumpPredsPriority()
H A DAMDGPUIGroupLP.cpp500 Succ->Preds, [&Pred](SDep &P) { return P.getSUnit() == Pred; }); in removeEdges()
1047 auto SuccSize = llvm::count_if(SU->Succs, [](const SDep &Succ) { in apply()
1048 return Succ.getKind() == SDep::Data; in apply()
1056 llvm::count_if(Succ.getSUnit()->Succs, [](const SDep &SuccSucc) { in apply()
1057 return SuccSucc.getKind() == SDep::Data; in apply()
1087 auto SuccSize = llvm::count_if(SU->Succs, [](const SDep &Succ) { in apply()
1088 return Succ.getKind() == SDep::Data; in apply()
1096 llvm::count_if(Succ.getSUnit()->Succs, [](const SDep &SuccSucc) { in apply()
1097 return SuccSucc.getKind() == SDep::Data; in apply()
1174 if (Succ.getSUnit() == SU && Succ.getKind() == SDep::Data) in apply()
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H A DGCNILPSched.cpp64 for (const SDep &Pred : SU->Preds) { in CalcNodeSethiUllmanNumber()
108 for (const SDep &Succ : SU->Succs) { in closestSucc()
123 for (const SDep &Pred : SU->Preds) { in calcMaxScratches()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMacroFusion.cpp34 static bool isHazard(const SDep &Dep) { in isHazard()
35 return Dep.getKind() == SDep::Anti || Dep.getKind() == SDep::Output; in isHazard()
39 for (const SDep &SI : SU.Preds) in getPredClusterSU()
57 for (SDep &SI : FirstSU.Succs) in fuseInstructionPair()
61 for (SDep &SI : SecondSU.Preds) in fuseInstructionPair()
74 if (!DAG.addEdge(&SecondSU, SDep(&FirstSU, SDep::Cluster))) in fuseInstructionPair()
94 for (SDep &SI : FirstSU.Succs) in fuseInstructionPair()
98 for (SDep &SI : SecondSU.Preds) in fuseInstructionPair()
111 for (const SDep &SI : FirstSU.Succs) { in fuseInstructionPair()
118 DAG.addEdge(SU, SDep(&SecondSU, SDep::Artificial)); in fuseInstructionPair()
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H A DScheduleDAG.cpp74 LLVM_DUMP_METHOD void SDep::dump(const TargetRegisterInfo *TRI) const { in dump()
106 bool SUnit::addPred(const SDep &D, bool Required) { in addPred()
108 for (SDep &PredDep : Preds) { in addPred()
119 SDep ForwardD = PredDep; in addPred()
121 for (SDep &SuccDep : PredSU->Succs) { in addPred()
136 SDep P = D; in addPred()
140 if (D.getKind() == SDep::Data) { in addPred()
175 void SUnit::removePred(const SDep &D) { in removePred()
177 SmallVectorImpl<SDep>::iterator I = llvm::find(Preds, D); in removePred()
181 SDep P = D; in removePred()
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H A DScheduleDAGInstrs.cpp284 SDep Dep; in addPhysRegDataDeps()
286 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
298 Dep = SDep(SU, SDep::Data, UseReg); in addPhysRegDataDeps()
331 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; in addPhysRegDeps()
341 (Kind != SDep::Output || !MO.isDead() || !DefMO.isDead())) { in addPhysRegDeps()
342 SDep Dep(SU, Kind, DefMO.getReg()); in addPhysRegDeps()
343 if (Kind != SDep::Anti) { in addPhysRegDeps()
475 SDep Dep(SU, SDep::Data, Reg); in addVRegDefDeps()
519 SDep Dep(SU, SDep::Output, Reg); in addVRegDefDeps()
567 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg)); in addVRegUseDeps()
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H A DAggressiveAntiDepBreaker.cpp256 static void AntiDepEdges(const SUnit *SU, std::vector<const SDep *> &Edges) { in AntiDepEdges()
258 for (const SDep &Pred : SU->Preds) { in AntiDepEdges()
259 if ((Pred.getKind() == SDep::Anti) || (Pred.getKind() == SDep::Output)) { in AntiDepEdges()
269 const SDep *Next = nullptr; in CriticalPathStep()
273 for (const SDep &Pred : SU->Preds) { in CriticalPathStep()
280 (NextDepth == PredTotalLatency && Pred.getKind() == SDep::Anti)) { in CriticalPathStep()
808 std::vector<const SDep *> Edges; in BreakAntiDependencies()
826 for (const SDep *Edge : Edges) { in BreakAntiDependencies()
829 if ((Edge->getKind() != SDep::Anti) && in BreakAntiDependencies()
830 (Edge->getKind() != SDep::Output)) continue; in BreakAntiDependencies()
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H A DCriticalAntiDepBreaker.cpp140 static const SDep *CriticalPathStep(const SUnit *SU) { in CriticalPathStep()
141 const SDep *Next = nullptr; in CriticalPathStep()
144 for (const SDep &P : SU->Preds) { in CriticalPathStep()
151 (NextDepth == PredTotalLatency && P.getKind() == SDep::Anti)) { in CriticalPathStep()
554 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) { in BreakAntiDependencies()
558 if (Edge->getKind() == SDep::Anti) { in BreakAntiDependencies()
577 for (const SDep &P : CriticalPathSU->Preds) in BreakAntiDependencies()
579 ? (P.getKind() != SDep::Anti || P.getReg() != AntiDepReg) in BreakAntiDependencies()
580 : (P.getKind() == SDep::Data && in BreakAntiDependencies()
H A DLatencyPriorityQueue.cpp58 for (const SDep &P : SU->Preds) { in getSingleUnscheduledPred()
76 for (const SDep &Succ : SU->Succs) in push()
90 for (const SDep &Succ : SU->Succs) in scheduledNode()
H A DMachinePipeliner.cpp939 if (SI.getKind() == SDep::Order) { in isSuccOrder()
1188 SmallVector<SDep, 4> RemoveDeps; in updatePhiDependences()
1213 SDep Dep(SU, SDep::Anti, Reg); in updatePhiDependences()
1221 I.addPred(SDep(SU, SDep::Barrier)); in updatePhiDependences()
1233 SDep Dep(SU, SDep::Data, Reg); in updatePhiDependences()
1243 I.addPred(SDep(SU, SDep::Barrier)); in updatePhiDependences()
1253 if (PMI->isPHI() && PI.getKind() == SDep::Order) { in updatePhiDependences()
1263 for (const SDep &D : RemoveDeps) in updatePhiDependences()
1302 SmallVector<SDep, 4> Deps; in changeDependences()
1303 for (const SDep &P : I.Preds) in changeDependences()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp83 void AddPred(SUnit *SU, const SDep &D) { SU->addPred(D); } in AddPred()
86 void RemovePred(SUnit *SU, const SDep &D) { SU->removePred(D); } in RemovePred()
89 void ReleasePred(SUnit *SU, SDep *PredEdge);
129 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { in ReleasePred()
152 for (SDep &Pred : SU->Preds) { in ReleasePredecessors()
182 for (SDep &Succ : SU->Succs) { in ScheduleNodeBottomUp()
267 SDep ChainPred; in CopyAndMoveSuccessors()
268 SmallVector<SDep, 4> ChainSuccs; in CopyAndMoveSuccessors()
269 SmallVector<SDep, 4> LoadPreds; in CopyAndMoveSuccessors()
270 SmallVector<SDep, 4> NodePreds; in CopyAndMoveSuccessors()
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H A DScheduleDAGRRList.cpp224 void AddPredQueued(SUnit *SU, const SDep &D) { in AddPredQueued()
232 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
240 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
251 void ReleasePred(SUnit *SU, const SDep *PredEdge);
258 void CapturePred(SDep *PredEdge);
400 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { in ReleasePred()
558 for (SDep &Pred : SU->Preds) { in ReleasePredecessors()
772 for (SDep &Succ : SU->Succs) { in ScheduleNodeBottomUp()
822 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) { in CapturePred()
841 for (SDep &Pred : SU->Preds) { in UnscheduleNodeBottomUp()
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H A DResourcePriorityQueue.cpp69 for (SDep &Pred : SU->Preds) { in numberRCValPredInSU()
107 for (const SDep &Succ : SU->Succs) { in numberRCValSuccInSU()
144 for (const SDep &Succ : SU->Succs) in numberCtrlDepsInSU()
153 for (SDep &Pred : SU->Preds) in numberCtrlPredInSU()
211 for (const SDep &Pred : SU->Preds) { in getSingleUnscheduledPred()
228 for (const SDep &Succ : SU->Succs) in push()
267 for (const SDep &Succ : S->Succs) { in isResourceAvailable()
497 for (SDep &Pred : SU->Preds) { in scheduledNode()
512 for (const SDep &Succ : SU->Succs) { in scheduledNode()
H A DScheduleDAGVLIW.cpp77 void releaseSucc(SUnit *SU, const SDep &D);
105 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { in releaseSucc()
131 for (SDep &Succ : SU->Succs) { in releaseSuccessors()
H A DScheduleDAGSDNodes.cpp510 SDep Dep = isChain ? SDep(OpSU, SDep::Barrier) in AddSchedEdges()
511 : SDep(OpSU, SDep::Data, PhysReg); in AddSchedEdges()
650 unsigned OpIdx, SDep& dep) const{ in computeOperandLatency()
655 if (dep.getKind() != SDep::Data) in computeOperandLatency()
812 for (const SDep &Pred : SU->Preds) { in EmitPhysRegCopy()
822 for (const SDep &Succ : SU->Succs) { in EmitPhysRegCopy()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h51 class SDep {
103 SDep() : Dep(nullptr, Data) {} in SDep() function
106 SDep(SUnit *S, Kind kind, Register Reg) : Dep(S, kind), Contents() { in SDep() function
123 SDep(SUnit *S, OrderKind kind) in SDep() function
129 bool overlaps(const SDep &Other) const;
131 bool operator==(const SDep &Other) const {
135 bool operator!=(const SDep &Other) const {
264 SmallVector<SDep, 4> Preds; ///< All sunit predecessors.
265 SmallVector<SDep, 4> Succs; ///< All sunit successors.
267 typedef SmallVectorImpl<SDep>::iterator pred_iterator;
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H A DMachinePipeliner.h121 SDep Pred;
130 SwingSchedulerDDGEdge(SUnit *PredOrSucc, const SDep &Dep, bool IsSucc, in SwingSchedulerDDGEdge()
142 if (Pred.getKind() == SDep::Anti && Src->getInstr()->isPHI()) { in SwingSchedulerDDGEdge()
146 Pred = SDep(Src, SDep::Kind::Data, Reg); in SwingSchedulerDDGEdge()
172 bool isAntiDep() const { return Pred.getKind() == SDep::Kind::Anti; } in isAntiDep()
175 bool isOutputDep() const { return Pred.getKind() == SDep::Kind::Output; } in isOutputDep()
179 bool isOrderDep() const { return Pred.getKind() == SDep::Kind::Order; } in isOrderDep()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLatencyMutations.h42 static void setBidirLatencies(SUnit &SrcSU, SDep &SrcDep, unsigned latency);
43 static bool zeroOutputDependences(SUnit &ISU, SDep &Dep);
44 unsigned makeBundleAssumptions(SUnit &ISU, SDep &Dep);
45 bool memoryRAWHazard(SUnit &ISU, SDep &Dep, unsigned latency);
H A DARMLatencyMutations.cpp491 void ARMOverrideBypasses::setBidirLatencies(SUnit &SrcSU, SDep &SrcDep, in setBidirLatencies()
493 SDep Reverse = SrcDep; in setBidirLatencies()
495 for (SDep &PDep : SrcDep.getSUnit()->Preds) { in setBidirLatencies()
513 bool ARMOverrideBypasses::zeroOutputDependences(SUnit &ISU, SDep &Dep) { in zeroOutputDependences()
514 if (Dep.getKind() == SDep::Output) { in zeroOutputDependences()
529 unsigned ARMOverrideBypasses::makeBundleAssumptions(SUnit &ISU, SDep &Dep) { in makeBundleAssumptions()
553 bool ARMOverrideBypasses::memoryRAWHazard(SUnit &ISU, SDep &Dep, in memoryRAWHazard()
613 for (SDep &Dep : ISU.Succs) { in modifyBypasses()
624 if (Dep.getKind() != SDep::Data) in modifyBypasses()
863 for (SDep &Dep : ISU.Succs) { in modifyBypasses()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp249 SmallVector<SDep, 4> Erase; in apply()
251 if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF) in apply()
269 for (SDep &SI : SU.Succs) { in apply()
270 if (SI.getKind() != SDep::Order || SI.getLatency() != 0) in apply()
279 for (SDep &PI : SI.getSUnit()->Preds) { in apply()
280 if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order) in apply()
328 DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier)); in apply()
332 DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier)); in apply()
368 SDep(It->second, SDep::Barrier)); in apply()
420 SDep A(&S0, SDep::Artificial); in apply()
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H A DHexagonVLIWPacketizer.cpp295 SDep::Kind DepType, unsigned DepReg) { in isCallDependent()
309 if (DepType == SDep::Data) { in isCallDependent()
318 static bool isRegDependence(const SDep::Kind DepType) { in isRegDependence()
319 return DepType == SDep::Data || DepType == SDep::Anti || in isRegDependence()
320 DepType == SDep::Output; in isRegDependence()
368 SDep::Kind DepType, MachineBasicBlock::iterator &MII, in promoteToDotCur()
370 assert(DepType == SDep::Data); in promoteToDotCur()
450 SDep::Kind DepType, MachineBasicBlock::iterator &MII, in promoteToDotNew()
452 assert(DepType == SDep::Data); in promoteToDotNew()
525 if (PI.getKind() != SDep::Anti && in updateOffset()
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H A DHexagonVLIWPacketizer.h119 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
121 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
129 bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorMaskDAGMutation.cpp50 SDep &Dep = SU.Succs[0]; in isSoleUseCopyToV0()
80 DAG->addEdge(&SU, SDep(NearestUseV0SU, SDep::Artificial)); in apply()

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