| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 347 case ISD::SDIV: in Select()
358 if (N->getOpcode() == ISD::SDIV) { in Select()
370 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips.h | 24 (instr == Mips::SDIV || instr == Mips::PseudoSDIV || instr == Mips::DSDIV || \
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| H A D | MipsFastISel.cpp | 1934 case ISD::SDIV: in selectDivRem()
1936 DivOpc = Mips::SDIV; in selectDivRem()
2052 if (!selectBinaryOp(I, ISD::SDIV)) in fastSelectInstruction()
2053 return selectDivRem(I, ISD::SDIV); in fastSelectInstruction()
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| H A D | MipsSEISelLowering.cpp | 276 setOperationAction(ISD::SDIV, MVT::i32, Legal); in MipsSETargetLowering()
323 setOperationAction(ISD::SDIV, MVT::i64, Legal); in MipsSETargetLowering()
375 setOperationAction(ISD::SDIV, Ty, Legal); in addMSAIntType()
1849 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsScheduleP5600.td | 192 def : InstRW<[P5600WriteAL2Div], (instrs DIV, PseudoSDIV, SDIV)>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiTargetTransformInfo.h | 107 case ISD::SDIV:
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| H A D | LanaiISelLowering.cpp | 104 setOperationAction(ISD::SDIV, MVT::i32, Expand); in LanaiTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPNodes.def | 100 ADD_BINARY_VVP_OP_COMPACT(SDIV)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 1386 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1390 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1394 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost}, in getArithmeticInstrCost()
1398 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
1403 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1407 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1411 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1415 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
2226 case ISD::SDIV: in maybeLoweredToCall()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 262 SDIV, enumerator
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| H A D | SDPatternMatch.h | 855 return BinaryOpc_match<LHS, RHS>(ISD::SDIV, L, R);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 341 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && in getArithmeticInstrCost()
440 { ISD::SDIV, MVT::v16i32, { 6 } }, // pmuludq sequence in getArithmeticInstrCost()
481 { ISD::SDIV, MVT::v8i32, { 6 } }, // pmuludq sequence in getArithmeticInstrCost()
522 { ISD::SDIV, MVT::v8i32, { 14 } }, // 2*pmuludq sequence + split. in getArithmeticInstrCost()
553 { ISD::SDIV, MVT::v4i32, { 6 } }, // pmuludq sequence in getArithmeticInstrCost()
568 { ISD::SDIV, MVT::v64i8, { 14 } }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
573 { ISD::SDIV, MVT::v32i16, { 6 } }, // vpmulhw sequence in getArithmeticInstrCost()
586 { ISD::SDIV, MVT::v64i8, { 28 } }, // 4*ext+4*pmulhw sequence in getArithmeticInstrCost()
591 { ISD::SDIV, MVT::v32i16, { 12 } }, // 2*vpmulhw sequence in getArithmeticInstrCost()
596 { ISD::SDIV, MVT::v16i32, { 15 } }, // vpmuldq sequence in getArithmeticInstrCost()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 111 setOperationAction(ISD::SDIV, VT, Custom); in BPFTargetLowering()
325 case ISD::SDIV: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 3965 case ISD::SDIV: in getArithmeticInstrCost()
4023 return ISD == ISD::SDIV ? (3 * AddCost + AsrCost) in getArithmeticInstrCost()
4037 (Op2Info.isNegatedPowerOf2() && ISD == ISD::SDIV) ? AsrCost : 0; in getArithmeticInstrCost()
4043 (ISD == ISD::SDIV in getArithmeticInstrCost()
4126 if (Ty->isVectorTy() && (ISD == ISD::SDIV || ISD == ISD::UDIV)) { in getArithmeticInstrCost()
4133 {ISD::SDIV, MVT::v2i8, 5}, {ISD::SDIV, MVT::v4i8, 8}, in getArithmeticInstrCost()
4134 {ISD::SDIV, MVT::v8i8, 8}, {ISD::SDIV, MVT::v2i16, 5}, in getArithmeticInstrCost()
4135 {ISD::SDIV, MVT::v4i16, 5}, {ISD::SDIV, MVT::v2i32, 1}, in getArithmeticInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 134 setOperationAction(ISD::SDIV, MVT::i8, Promote); in MSP430TargetLowering()
140 setOperationAction(ISD::SDIV, MVT::i16, LibCall); in MSP430TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 78 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i8, Promote); in M68kTargetLowering()
79 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i16, Legal); in M68kTargetLowering()
81 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, Legal); in M68kTargetLowering()
83 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, LibCall); in M68kTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 152 setOperationAction(ISD::SDIV, MVT::i32, Legal); in XtensaTargetLowering()
157 setOperationAction(ISD::SDIV, MVT::i32, Expand); in XtensaTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 985 case ISD::SDIV: in canOpTrap()
1868 case SDiv: return ISD::SDIV; in InstructionOpcodeToISD()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 284 case ISD::SDIV: return "sdiv"; in getOperationName()
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| H A D | FastISel.cpp | 491 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) && in selectBinaryOp()
1763 return selectBinaryOp(I, ISD::SDIV); in selectOperator()
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| H A D | LegalizeDAG.cpp | 3916 case ISD::SDIV: { in ExpandNode()
3917 bool isSigned = Node->getOpcode() == ISD::SDIV; in ExpandNode()
5169 case ISD::SDIV: in ConvertNodeToLibcall()
5439 case ISD::SDIV: in PromoteNode()
5461 case ISD::SDIV: in PromoteNode()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 161 HELPER_REGISTER_BINARY_INT_VP(vp_sdiv, VP_SDIV, SDiv, SDIV)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 154 setOperationAction(ISD::SDIV, MVT::i8, Expand); in AVRTargetLowering()
155 setOperationAction(ISD::SDIV, MVT::i16, Expand); in AVRTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 159 setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM}, MVT::i32, in LoongArchTargetLowering()
300 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
367 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
3787 case ISD::SDIV: in getLoongArchWOpcode()
4026 case ISD::SDIV: in ReplaceNodeResults()
5418 return DAG.getNode(ISD::SDIV, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 106 setOperationAction(ISD::SDIV, MVT::i32, Expand); in CSKYTargetLowering()
|