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Searched refs:ResVT (Results 1 – 25 of 35) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.h164 SDValue getNode(unsigned OC, ArrayRef<EVT> ResVT, ArrayRef<SDValue> OpV,
166 auto N = DAG.getNode(OC, DL, ResVT, OpV);
172 SDValue getNode(unsigned OC, EVT ResVT, ArrayRef<SDValue> OpV,
174 auto N = DAG.getNode(OC, DL, ResVT, OpV);
184 SDValue getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, SDValue StartV,
H A DVVPInstrPatternsVec.td598 RegisterClass ResRC, ValueType ResVT,
601 def : Pat <(ResVT (!cast<SDPatternOperator>("vvp_reduce_"#VVPRedOp)
609 def : Pat <(ResVT (!cast<SDPatternOperator>("vvp_reduce_"#VVPRedOp)
618 RegisterClass ResRC, ValueType ResVT,
620 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "or", "VROR">;
621 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "and", "VRAND">;
622 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "xor", "VRXOR">;
623 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "add", "VSUM"#SumSuffix>;
624 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "smax", "VRMAX"#MinMaxSuffix>;
H A DVECustomDAG.cpp562 SDValue VECustomDAG::getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, in getLegalReductionOpVVP() argument
576 return getNode(ScalarOC, ResVT, {StartV, ReductionResV}); in getLegalReductionOpVVP()
583 getNode(VVPOpcode, ResVT, {StartV, VectorV, Mask, AVL}, Flags)); in getLegalReductionOpVVP()
586 getNode(VVPOpcode, ResVT, {VectorV, Mask, AVL}, Flags)); in getLegalReductionOpVVP()
H A DVVPISelLowering.cpp351 MVT ResVT = splitVectorType(Op.getValue(0).getSimpleValueType()); in splitVectorOp()
394 CDAG.getNode(Op.getOpcode(), ResVT, OpVec, Op->getFlags()); in splitVectorOp()
345 MVT ResVT = splitVectorType(Op.getValue(0).getSimpleValueType()); splitVectorOp() local
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2512 EVT ResVT = N->getValueType(0); in performVectorExtendToFPCombine() local
2514 if (ResVT == MVT::v4f32 && (InVT == MVT::v4i16 || InVT == MVT::v4i8)) in performVectorExtendToFPCombine()
2516 else if (ResVT == MVT::v2f64 && (InVT == MVT::v2i16 || InVT == MVT::v2i8)) in performVectorExtendToFPCombine()
2524 return DAG.getNode(N->getOpcode(), SDLoc(N), ResVT, Conv); in performVectorExtendToFPCombine()
2546 EVT ResVT = N->getValueType(0); in performVectorExtendCombine() local
2547 if (ResVT == MVT::v8i16) { in performVectorExtendCombine()
2551 } else if (ResVT == MVT::v4i32) { in performVectorExtendCombine()
2555 } else if (ResVT == MVT::v2i64) { in performVectorExtendCombine()
2571 return DAG.getNode(Op, SDLoc(N), ResVT, Source); in performVectorExtendCombine()
2615 EVT ResVT; in performVectorTruncZeroCombine() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp347 EVT ResVT = N->getValueType(0); in ScalarizeVecRes_OverflowOp()
351 if (getTypeAction(ResVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_OverflowOp()
363 ResVT.getVectorElementType(), OvVT.getVectorElementType()); in ScalarizeVecRes_OverflowOp()
1043 EVT ResVT = N->getValueType(0).getVectorElementType();
1044 SDValue Cmp = DAG.getNode(N->getOpcode(), SDLoc(N), ResVT, LHS, RHS);
1865 EVT ResVT = N->getValueType(0); in SplitVecRes_OverflowOp()
1868 std::tie(LoResVT, HiResVT) = DAG.GetSplitDestVTs(ResVT); in SplitVecRes_OverflowOp()
1872 if (getTypeAction(ResVT) == TargetLowering::TypeSplitVector) { in SplitVecRes_OverflowOp()
3323 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE()
3338 return DAG.getNode(N->getOpcode(), dl, ResVT, Partia in SplitVecOp_VECREDUCE_SEQ() local
343 EVT ResVT = N->getValueType(0); ScalarizeVecRes_OverflowOp() local
1039 EVT ResVT = N->getValueType(0).getVectorElementType(); ScalarizeVecOp_CMP() local
1861 EVT ResVT = N->getValueType(0); SplitVecRes_OverflowOp() local
3319 EVT ResVT = N->getValueType(0); SplitVecOp_VECREDUCE() local
3364 EVT ResVT = N->getValueType(0); SplitVecOp_VP_REDUCE() local
3388 EVT ResVT = N->getValueType(0); SplitVecOp_UnaryOp() local
3431 EVT ResVT = N->getValueType(0); SplitVecOp_BITCAST() local
3456 EVT ResVT = N->getValueType(0); SplitVecOp_INSERT_SUBVECTOR() local
4153 EVT ResVT = N->getValueType(0); SplitVecOp_FP_ROUND() local
4222 EVT ResVT = N->getValueType(0); SplitVecOp_CMP() local
4234 EVT ResVT = N->getValueType(0); SplitVecOp_FP_TO_XINT_SAT() local
4252 EVT ResVT = N->getValueType(0); SplitVecOp_VP_CttzElements() local
4967 EVT ResVT = N->getValueType(0); WidenVecRes_OverflowOp() local
6559 EVT ResVT = N->getValueType(0); WidenVecOp_CMP() local
6604 EVT ResVT = WidenVecOp_IS_FPCLASS() local
7119 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), WidenVecOp_SETCC() local
[all...]
H A DLegalizeIntegerTypes.cpp368 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0() local
370 N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
2608 EVT ResVT = N->getValueType(0); in PromoteIntOp_VECREDUCE() local
2656 if (ResVT.bitsGE(EltVT)) in PromoteIntOp_VECREDUCE()
2657 return DAG.getNode(Opcode, SDLoc(N), ResVT, Op); in PromoteIntOp_VECREDUCE()
2662 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, Reduce); in PromoteIntOp_VECREDUCE()
5714 EVT ResVT = V0.getValueType(); in PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE() local
5716 DAG.getVTList(ResVT, ResVT), V0, V1); in PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE()
6113 EVT ResVT = N->getValueType(0); in PromoteIntOp_CONCAT_VECTORS() local
6116 if (ResVT.isScalableVector()) { in PromoteIntOp_CONCAT_VECTORS()
[all …]
H A DSelectionDAG.cpp2058 SDValue SelectionDAG::getStepVector(const SDLoc &DL, EVT ResVT) { in getStepVector() argument
2059 APInt One(ResVT.getScalarSizeInBits(), 1); in getStepVector()
2060 return getStepVector(DL, ResVT, One); in getStepVector()
2063 SDValue SelectionDAG::getStepVector(const SDLoc &DL, EVT ResVT, in getStepVector() argument
2065 assert(ResVT.getScalarSizeInBits() == StepVal.getBitWidth()); in getStepVector()
2066 if (ResVT.isScalableVector()) in getStepVector()
2068 ISD::STEP_VECTOR, DL, ResVT, in getStepVector()
2069 getTargetConstant(StepVal, DL, ResVT.getVectorElementType())); in getStepVector()
2072 for (uint64_t i = 0; i < ResVT.getVectorNumElements(); i++) in getStepVector()
2074 getConstant(StepVal * i, DL, ResVT.getVectorElementType())); in getStepVector()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp6053 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
6056 assert(ResVT.isVector() && "Vector load must have vector type"); in ReplaceLoadVector()
6061 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
6062 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
6099 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
6100 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
6183 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
6190 SDValue BuildVec = DAG.getBuildVector(ResVT, DL, ScalarRes); in ReplaceLoadVector()
6213 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
6215 if (ResVT.isVector()) { in ReplaceINTRINSIC_W_CHAIN()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1771 EVT ResVT = TLI->getValueType(DL, ResTy); in getExtendedReductionCost() local
1777 if (ST->hasMVEIntegerOps() && ValVT.isSimple() && ResVT.isSimple()) { in getExtendedReductionCost()
1786 unsigned RevVTSize = ResVT.getSizeInBits(); in getExtendedReductionCost()
1806 EVT ResVT = TLI->getValueType(DL, ResTy); in getMulAccReductionCost() local
1808 if (ST->hasMVEIntegerOps() && ValVT.isSimple() && ResVT.isSimple()) { in getMulAccReductionCost()
1817 unsigned RevVTSize = ResVT.getSizeInBits(); in getMulAccReductionCost()
H A DARMISelLowering.cpp17101 EVT ResVT = N->getValueType(0); in PerformVECREDUCE_ADDCombine() local
17106 if (ResVT == MVT::i32 && N0.getOpcode() == ISD::ADD && in PerformVECREDUCE_ADDCombine()
17109 SDValue Red0 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(0)); in PerformVECREDUCE_ADDCombine()
17110 SDValue Red1 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(1)); in PerformVECREDUCE_ADDCombine()
17111 return DAG.getNode(ISD::ADD, dl, ResVT, Red0, Red1); in PerformVECREDUCE_ADDCombine()
17145 if (ResVT != RetTy || N0->getOpcode() != ExtendCode) in PerformVECREDUCE_ADDCombine()
17154 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
17176 if (ResVT != RetTy) in PerformVECREDUCE_ADDCombine()
17181 ResVT.getScalarSizeInBits()) in PerformVECREDUCE_ADDCombine()
17206 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
[all …]
H A DARMISelLowering.h618 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1954 bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT, in shouldExpandGetActiveLaneMask() argument
1962 if (ResVT != MVT::nxv2i1 && ResVT != MVT::nxv4i1 && ResVT != MVT::nxv8i1 && in shouldExpandGetActiveLaneMask()
1963 ResVT != MVT::nxv16i1 && ResVT != MVT::v2i1 && ResVT != MVT::v4i1 && in shouldExpandGetActiveLaneMask()
1964 ResVT != MVT::v8i1 && ResVT != MVT::v16i1) in shouldExpandGetActiveLaneMask()
6052 EVT ResVT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN() local
6053 if (ResVT == MVT::i32 && (OpVT == MVT::v8i8 || OpVT == MVT::v16i8 || in LowerINTRINSIC_WO_CHAIN()
14847 static bool canLowerSRLToRoundingShiftForVT(SDValue Shift, EVT ResVT, in canLowerSRLToRoundingShiftForVT() argument
14863 if (ShiftValue < 1 || ShiftValue > ResVT.getScalarSizeInBits()) in canLowerSRLToRoundingShiftForVT()
14870 assert(ResVT.getScalarSizeInBits() <= VT.getScalarSizeInBits() && in canLowerSRLToRoundingShiftForVT()
14873 uint64_t ExtraBits = VT.getScalarSizeInBits() - ResVT.getScalarSizeInBits(); in canLowerSRLToRoundingShiftForVT()
[all …]
H A DAArch64ISelLowering.h774 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3834 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
3841 SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(), in lowerBITCAST()
3848 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3864 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
6526 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT, in combineExtract() argument
6554 return DAG.getUNDEF(ResVT); in combineExtract()
6584 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract()
6586 if (VT != ResVT) { in combineExtract()
6588 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op); in combineExtract()
6624 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h170 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DHexagonISelLowering.cpp2180 bool HexagonTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
2182 assert(ResVT.getVectorElementType() == SrcVT.getVectorElementType()); in isExtractSubvectorCheap()
2183 if (!ResVT.isSimple() || !SrcVT.isSimple()) in isExtractSubvectorCheap()
2186 MVT ResTy = ResVT.getSimpleVT(), SrcTy = SrcVT.getSimpleVT(); in isExtractSubvectorCheap()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h362 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DSIISelLowering.cpp1928 bool SITargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
1930 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
5741 auto ResVT = DAG.GetSplitDestVTs(VT); in splitTernaryVectorOp() local
5743 SDValue OpLo = DAG.getNode(Opc, SL, ResVT.first, Lo0, Lo1, Lo2, in splitTernaryVectorOp()
5745 SDValue OpHi = DAG.getNode(Opc, SL, ResVT.second, Hi0, Hi1, Hi2, in splitTernaryVectorOp()
13379 EVT ResVT = N->getValueType(0); in performExtractVectorEltCombine() local
13389 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, ResVT, Vec.getOperand(0), Idx); in performExtractVectorEltCombine()
13390 return DAG.getNode(Vec.getOpcode(), SL, ResVT, Elt); in performExtractVectorEltCombine()
13398 if (Vec.hasOneUse() && DCI.isBeforeLegalize() && VecEltVT == ResVT) { in performExtractVectorEltCombine()
13421 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, ResVT, in performExtractVectorEltCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp3618 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3619 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3620 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3625 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt; in fastLowerCall()
H A DX86ISelLowering.cpp3195 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
3197 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
3202 if (ResVT.getVectorElementType() == MVT::i1) in isExtractSubvectorCheap()
3203 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) && in isExtractSubvectorCheap()
3204 (Index == ResVT.getVectorNumElements())); in isExtractSubvectorCheap()
3206 return (Index % ResVT.getVectorNumElements()) == 0; in isExtractSubvectorCheap()
9217 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
9219 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
9220 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); in LowerAVXCONCAT_VECTORS()
9249 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in LowerAVXCONCAT_VECTORS()
[all …]
H A DX86ISelLowering.h1449 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h526 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8164 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
8209 ResVT == MVT::f128) in LowerSELECT_CC()
8224 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
8227 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
8237 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
8246 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
8260 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
8263 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
8270 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
8276 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h898 SDValue getStepVector(const SDLoc &DL, EVT ResVT, const APInt &StepVal);
902 SDValue getStepVector(const SDLoc &DL, EVT ResVT);

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