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Searched refs:ResVT (Results 1 – 25 of 39) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.h164 SDValue getNode(unsigned OC, ArrayRef<EVT> ResVT, ArrayRef<SDValue> OpV,
166 auto N = DAG.getNode(OC, DL, ResVT, OpV);
172 SDValue getNode(unsigned OC, EVT ResVT, ArrayRef<SDValue> OpV,
174 auto N = DAG.getNode(OC, DL, ResVT, OpV);
184 SDValue getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, SDValue StartV,
H A DVVPInstrPatternsVec.td598 RegisterClass ResRC, ValueType ResVT,
601 def : Pat <(ResVT (!cast<SDPatternOperator>("vvp_reduce_"#VVPRedOp)
609 def : Pat <(ResVT (!cast<SDPatternOperator>("vvp_reduce_"#VVPRedOp)
618 RegisterClass ResRC, ValueType ResVT,
620 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "or", "VROR">;
621 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "and", "VRAND">;
622 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "xor", "VRXOR">;
623 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "add", "VSUM"#SumSuffix>;
624 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "smax", "VRMAX"#MinMaxSuffix>;
H A DVECustomDAG.cpp562 SDValue VECustomDAG::getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, in getLegalReductionOpVVP() argument
576 return getNode(ScalarOC, ResVT, {StartV, ReductionResV}); in getLegalReductionOpVVP()
583 getNode(VVPOpcode, ResVT, {StartV, VectorV, Mask, AVL}, Flags)); in getLegalReductionOpVVP()
586 getNode(VVPOpcode, ResVT, {VectorV, Mask, AVL}, Flags)); in getLegalReductionOpVVP()
H A DVVPISelLowering.cpp351 MVT ResVT = splitVectorType(Op.getValue(0).getSimpleValueType()); in splitVectorOp()
394 CDAG.getNode(Op.getOpcode(), ResVT, OpVec, Op->getFlags()); in splitVectorOp()
345 MVT ResVT = splitVectorType(Op.getValue(0).getSimpleValueType()); splitVectorOp() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp358 EVT ResVT = N->getValueType(0); in ScalarizeVecRes_OverflowOp() local
362 if (getTypeAction(ResVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_OverflowOp()
374 ResVT.getVectorElementType(), OvVT.getVectorElementType()); in ScalarizeVecRes_OverflowOp()
1090 EVT ResVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecOp_CMP() local
1091 SDValue Cmp = DAG.getNode(N->getOpcode(), SDLoc(N), ResVT, LHS, RHS); in ScalarizeVecOp_CMP()
1941 EVT ResVT = N->getValueType(0); in SplitVecRes_OverflowOp() local
1944 std::tie(LoResVT, HiResVT) = DAG.GetSplitDestVTs(ResVT); in SplitVecRes_OverflowOp()
1948 if (getTypeAction(ResVT) == TargetLowering::TypeSplitVector) { in SplitVecRes_OverflowOp()
3625 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE() local
3640 return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags()); in SplitVecOp_VECREDUCE()
[all …]
H A DSelectionDAG.cpp2115 SDValue SelectionDAG::getStepVector(const SDLoc &DL, EVT ResVT) { in getStepVector() argument
2116 APInt One(ResVT.getScalarSizeInBits(), 1); in getStepVector()
2117 return getStepVector(DL, ResVT, One); in getStepVector()
2120 SDValue SelectionDAG::getStepVector(const SDLoc &DL, EVT ResVT, in getStepVector() argument
2122 assert(ResVT.getScalarSizeInBits() == StepVal.getBitWidth()); in getStepVector()
2123 if (ResVT.isScalableVector()) in getStepVector()
2125 ISD::STEP_VECTOR, DL, ResVT, in getStepVector()
2126 getTargetConstant(StepVal, DL, ResVT.getVectorElementType())); in getStepVector()
2129 for (uint64_t i = 0; i < ResVT.getVectorNumElements(); i++) in getStepVector()
2131 getConstant(StepVal * i, DL, ResVT.getVectorElementType())); in getStepVector()
[all …]
H A DLegalizeIntegerTypes.cpp388 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0() local
407 DAG.getAtomicLoad(ExtType, SDLoc(N), N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
2744 EVT ResVT = N->getValueType(0); in PromoteIntOp_VECREDUCE() local
2792 if (ResVT.bitsGE(EltVT)) in PromoteIntOp_VECREDUCE()
2793 return DAG.getNode(Opcode, SDLoc(N), ResVT, Op); in PromoteIntOp_VECREDUCE()
2798 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, Reduce); in PromoteIntOp_VECREDUCE()
6390 EVT ResVT = N->getValueType(0); in PromoteIntOp_CONCAT_VECTORS() local
6393 if (ResVT.isScalableVector()) { in PromoteIntOp_CONCAT_VECTORS()
6394 SDValue ResVec = DAG.getUNDEF(ResVT); in PromoteIntOp_CONCAT_VECTORS()
6399 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op, in PromoteIntOp_CONCAT_VECTORS()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2922 EVT ResVT = N->getValueType(0); in performVectorExtendToFPCombine() local
2924 if (ResVT == MVT::v4f32 && (InVT == MVT::v4i16 || InVT == MVT::v4i8)) in performVectorExtendToFPCombine()
2926 else if (ResVT == MVT::v2f64 && (InVT == MVT::v2i16 || InVT == MVT::v2i8)) in performVectorExtendToFPCombine()
2934 return DAG.getNode(N->getOpcode(), SDLoc(N), ResVT, Conv); in performVectorExtendToFPCombine()
2956 EVT ResVT = N->getValueType(0); in performVectorExtendCombine() local
2957 if (ResVT == MVT::v8i16) { in performVectorExtendCombine()
2961 } else if (ResVT == MVT::v4i32) { in performVectorExtendCombine()
2965 } else if (ResVT == MVT::v2i64) { in performVectorExtendCombine()
2981 return DAG.getNode(Op, SDLoc(N), ResVT, Source); in performVectorExtendCombine()
3025 EVT ResVT; in performVectorTruncZeroCombine() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp5862 const EVT ResVT = LD->getValueType(0); in replaceLoadVector() local
5867 if (ResVT != MemVT) in replaceLoadVector()
5871 ResVT, STI.has256BitVectorLoadStore(LD->getAddressSpace())); in replaceLoadVector()
5926 assert(EVT(EltVT.getVectorElementType()) == ResVT.getVectorElementType()); in replaceLoadVector()
5928 ResVT.getVectorNumElements()); in replaceLoadVector()
5949 SDValue LoadValue = DAG.getBitcast(ResVT, BuildVec); in replaceLoadVector()
5959 EVT ResVT = N->getValueType(0); in ReplaceTcgen05Ld() local
5960 if (!ResVT.isVector()) in ReplaceTcgen05Ld()
5963 const unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceTcgen05Ld()
5996 SDValue BuildVector = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes); in ReplaceTcgen05Ld()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2138 bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT, in shouldExpandGetActiveLaneMask() argument
2142 ResVT.getVectorElementType() != MVT::i1) in shouldExpandGetActiveLaneMask()
2146 if (ResVT.getVectorMinNumElements() == 1 || in shouldExpandGetActiveLaneMask()
2147 (ResVT.isFixedLengthVector() && (ResVT.getVectorNumElements() > 16 || in shouldExpandGetActiveLaneMask()
5725 EVT ResVT = Op.getValueType(); in LowerVectorMatch() local
5742 if (ResVT.isScalableVector()) in LowerVectorMatch()
5758 if (ResVT.isScalableVector()) in LowerVectorMatch()
5759 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, ResVT, ID, Mask, Op1, Op2); in LowerVectorMatch()
5777 return DAG.getNode(ISD::TRUNCATE, DL, ResVT, Match); in LowerVectorMatch()
6340 EVT ResVT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN() local
[all …]
H A DAArch64ISelLowering.h295 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DAArch64TargetTransformInfo.cpp5301 EVT ResVT = TLI->getValueType(DL, ResTy); in getExtendedReductionCost() local
5303 if (Opcode == Instruction::Add && VecVT.isSimple() && ResVT.isSimple() && in getExtendedReductionCost()
5310 unsigned RevVTSize = ResVT.getSizeInBits(); in getExtendedReductionCost()
5329 EVT ResVT = TLI->getValueType(DL, ResTy); in getMulAccReductionCost() local
5331 if (ST->hasDotProd() && VecVT.isSimple() && ResVT.isSimple()) { in getMulAccReductionCost()
5338 ResVT == MVT::i32) in getMulAccReductionCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1854 EVT ResVT = TLI->getValueType(DL, ResTy); in getExtendedReductionCost() local
1860 if (ST->hasMVEIntegerOps() && ValVT.isSimple() && ResVT.isSimple()) { in getExtendedReductionCost()
1869 unsigned RevVTSize = ResVT.getSizeInBits(); in getExtendedReductionCost()
1889 EVT ResVT = TLI->getValueType(DL, ResTy); in getMulAccReductionCost() local
1891 if (ST->hasMVEIntegerOps() && ValVT.isSimple() && ResVT.isSimple()) { in getMulAccReductionCost()
1900 unsigned RevVTSize = ResVT.getSizeInBits(); in getMulAccReductionCost()
H A DARMISelLowering.cpp17174 EVT ResVT = N->getValueType(0); in PerformVECREDUCE_ADDCombine() local
17179 if (ResVT == MVT::i32 && N0.getOpcode() == ISD::ADD && in PerformVECREDUCE_ADDCombine()
17182 SDValue Red0 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(0)); in PerformVECREDUCE_ADDCombine()
17183 SDValue Red1 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(1)); in PerformVECREDUCE_ADDCombine()
17184 return DAG.getNode(ISD::ADD, dl, ResVT, Red0, Red1); in PerformVECREDUCE_ADDCombine()
17218 if (ResVT != RetTy || N0->getOpcode() != ExtendCode) in PerformVECREDUCE_ADDCombine()
17227 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
17249 if (ResVT != RetTy) in PerformVECREDUCE_ADDCombine()
17254 ResVT.getScalarSizeInBits()) in PerformVECREDUCE_ADDCombine()
17279 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
[all …]
H A DARMISelLowering.h639 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4287 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
4294 SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(), in lowerBITCAST()
4301 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
4317 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
7285 EVT ResVT = N->getValueType(0); in LowerOperationWrapper() local
7286 if (ResVT == MVT::i128 && SrcVT == MVT::f128) in LowerOperationWrapper()
7288 else if (SrcVT == MVT::i16 && ResVT == MVT::f16) { in LowerOperationWrapper()
7297 } else if (SrcVT == MVT::f16 && ResVT == MVT::i16) { in LowerOperationWrapper()
7303 Results.push_back(DAG.getZExtOrTrunc(ExtractedVal, DL, ResVT)); in LowerOperationWrapper()
7316 EVT ResVT = N->getValueType(0); in LowerOperationWrapper() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h67 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DRISCVISelLowering.cpp2340 bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
2342 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
2350 if (ResVT.isScalableVector() || SrcVT.isScalableVector()) in isExtractSubvectorCheap()
2353 EVT EltVT = ResVT.getVectorElementType(); in isExtractSubvectorCheap()
2361 unsigned ResElts = ResVT.getVectorNumElements(); in isExtractSubvectorCheap()
4851 MVT ResVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), in getDeinterleaveShiftAndTrunc() local
4858 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT, Res); in getDeinterleaveShiftAndTrunc()
4859 MVT CastVT = ResVT.changeVectorElementType(VT.getVectorElementType()); in getDeinterleaveShiftAndTrunc()
11193 static SDValue lowerReductionSeq(unsigned RVVOpcode, MVT ResVT, in lowerReductionSeq() argument
11218 return DAG.getExtractVectorElt(DL, ResVT, Reduction, 0); in lowerReductionSeq()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h375 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DSIISelLowering.cpp2040 bool SITargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
2042 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
6090 auto ResVT = DAG.GetSplitDestVTs(VT); in splitTernaryVectorOp() local
6093 DAG.getNode(Opc, SL, ResVT.first, Lo0, Lo1, Lo2, Op->getFlags()); in splitTernaryVectorOp()
6095 DAG.getNode(Opc, SL, ResVT.second, Hi0, Hi1, Hi2, Op->getFlags()); in splitTernaryVectorOp()
14192 EVT ResVT = N->getValueType(0); in performExtractVectorEltCombine() local
14202 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, ResVT, Vec.getOperand(0), Idx); in performExtractVectorEltCombine()
14203 return DAG.getNode(Vec.getOpcode(), SL, ResVT, Elt); in performExtractVectorEltCombine()
14211 if (Vec.hasOneUse() && DCI.isBeforeLegalize() && VecEltVT == ResVT) { in performExtractVectorEltCombine()
14234 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, ResVT, in performExtractVectorEltCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h170 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DHexagonISelLowering.cpp2202 bool HexagonTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
2204 assert(ResVT.getVectorElementType() == SrcVT.getVectorElementType()); in isExtractSubvectorCheap()
2205 if (!ResVT.isSimple() || !SrcVT.isSimple()) in isExtractSubvectorCheap()
2208 MVT ResTy = ResVT.getSimpleVT(), SrcTy = SrcVT.getSimpleVT(); in isExtractSubvectorCheap()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp3659 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3660 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3661 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3666 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt; in fastLowerCall()
H A DX86ISelLowering.cpp3371 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
3373 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
3378 if (ResVT.getVectorElementType() == MVT::i1) in isExtractSubvectorCheap()
3379 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) && in isExtractSubvectorCheap()
3380 (Index == ResVT.getVectorNumElements())); in isExtractSubvectorCheap()
3382 return (Index % ResVT.getVectorNumElements()) == 0; in isExtractSubvectorCheap()
9618 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
9619 assert((ResVT.is256BitVector() || ResVT.is512BitVector()) && in LowerAVXCONCAT_VECTORS()
9652 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in LowerAVXCONCAT_VECTORS()
9658 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in LowerAVXCONCAT_VECTORS()
[all …]
H A DX86ISelLowering.h1536 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,

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